M16CSLASH29 datasheet(114/499 Pages) RENESAS

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10. Watchdog Timer

page 90

Figure 10.2 WDC Register and WDTS Register

10.1 Count Source Protective Mode

In this mode, a on-chip oscillator clock is used for the watchdog timer count source. The watchdog timer

can be kept being clocked even when CPU clock stops as a result of run-away.

Before this mode can be used, the following register settings are required:

(1) Set the PRC1 bit in the PRCR register to 1 (enable writes to PM1 and PM2 registers).

(2) Set the PM12 bit in the PM1 register to 1 (reset when the watchdog timer underflows).

(3) Set the PM22 bit in the PM2 register to 1 (on-chip oscillator clock used for the watchdog timer count source).

(4) Set the PRC1 bit in the PRCR register to 0 (disable writes to PM1 and PM2 registers).

(5) Write to the WDTS register (watchdog timer starts counting).

Setting the PM22 bit to 1 results in the following conditions

• The on-chip oscillator continues oscillating even if the CM21 bit in the CM2 register is set to "0" (main clock

or PLL clock) (system clock of count source selected by the CM21 bit is valid)

• The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer

count source.

• The CM10 bit in the CM1 register is disabled against write. (Writing a 1 has no effect, nor is stop mode entered.)

• The watchdog timer does not stop when in wait mode.

Watchdog timer period =

Watchdog timer count (32768)

on-chip oscillator clock

Watchdog Timer Start Register

Symbol

Address

After Reset

WDTS

000E16

Undefined

Function

The watchdog timer is initialized and starts counting after a write instruction

to this register. The watchdog timer value is always initialized to 7FFF16

regardless of whatever value is written.

Watchdog Timer Control Register

Symbol

Address

After Reset

WDC

000F16

00XXXXXX2

Function

Bit Symbol

b7 b6 b5 b4 b3 b2 b1 b0

High-order bits of watchdog timer

WDC7

Bit Name

Prescaler select bit

0 : Divided by 16

1 : Divided by 128

Reserved bit

Set to 0

(b4-b0)

(b6)

(b5)

Reserved bit

Set to 0

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