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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ORSPI4 датащи(PDF) 162 Page - Lattice Semiconductor |
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ORSPI4 датащи(HTML) 162 Page - Lattice Semiconductor |
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162 / 263 page  Lattice Semiconductor ORCA ORSPI4 Data Sheet 162 30907 A 30A07 B [0:1] RX_DPRAM_0_AGG R_MODE 00 RX bank 0 aggregation mode 00 = 32 bit data 01 = 64 bit data 10 = 128 bit data 11 = not valid [2:3] RX_DPRAM_1_AGG R_MODE RX bank 1 aggregation mode [4:5] RX_DPRAM_2_AGG R_MODE RX bank 2 aggregation mode [6:7] RX_DPRAM_3_AGG R_MODE RX bank 3 aggregation mode 30910 A 30A10 B [0] Reserved [1:3] RX_DIP4_ERR_TH 00 Number of consecutive bad/good DIP-4 code words for SPI4 RX to lose/gain alignment. Loss of alignment is indicated by RX_ALGN_OFF_STS [4] RX_DISABLE_STAT US Causes 11 word to be sent on RX status frame. In turn causes far-end TX to cancel all credits and send a training pattern. [5] RX_MASK_DIP4 Allows SPI4 link to be used in presence of errors on data input. [6] RX_EN_TRAINING Enable detection of training patterns on the RX side. [7] RX_EN_BASELINE Enable RX baseline process 30911 A 30A11 B [0:7] RX_FIFO_THRESHO LD_H 00 High watermark threshold for async FIFO within RDP. 30912 A 30A12 B [0:3] RX_DPRAM_FIFO_ OVERRUN_INT_EN 00 These bits act as an enable for the status flags and the interrupts regarding overrun of the 4 RX DPRAM FIFO banks. [4:7] RX_DPRAM_FIFO_U RRUN_INT_EN These bits act as an enable for the status flags and the interrupts regarding underrun of the 4 RX DPRAM FIFO banks. 30913 A 30A13 B [0] RX_PLL_LOL_INT_E N 00 This bit enables the status flag and the interrupt regarding loss of lock in the SPI4 core (high-speed macrocell) PLL. See RX_PLL_LOL_STS in register 3091C[A], 3091C[B]. [1] RX_BAS_DONE_INT _EN This bit enables the status flag and the interrupt for the SPI4 core when RDI completes the baselining process. Baselining is the self-alignment power-up process that the macro does after it detects lock of the PLL. See RX_BAS_DONE_STS in register 3091C[A], 3091C[B]. [2] RX_BAS_ERR_INT_ EN This bit enables the status flag and the interrupt for the SPI4 core when RDI fails its internal self-alignment process. See RX_BAS_ERR_STS in register 3091C[A], 3091C[B]. [3] RX_DSKW_DONE_I NT_EN This bit enables the status flag and the interrupt for the SPI4 core when RDI completes its dynamic alignment process. See RX_DSKW_DONE_STS in register 3091C[A], 3091C[B]. [4] RX_DSKW_ERR_IN T_EN This bit enables the status flag and the interrupt for the SPI4 core when RDI fails to dynamically align. See RX_DSKW_ERR_STS in register 3091C[A], 3091C[B]. [5] RX_TRN_DET_INT_ EN This bit enables the status flag and the interrupt for the SPI4 core when RDI detects training patterns. See RX_TRN_DET_STS in register 3091C[A], 3091C[B]. [6] RX_ALGN_OFF_INT _EN This bit enables the status flag and the interrupt for the SPI4 core loss of RX alignment due to excess consecutive DIP4 errors. See RX_ALGN_OFF_STS in register 3091C[A], 3091C[B]. [7] TX_STATUS_LOF_IN T_EN This bit enables the status flag and the interrupt for the SPI4 core TX status from having too many consecutive DIP2 errors. See TX_STATUS_LOF_STS Table 47. Memory Map (Continued) (0x) Abso- lute Address Bit Name Reset Value (0x) Description |
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