ORSPI4 datasheet(161/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

161

30805

[0]A

[1]B

[2]C

[3]D

DEMUXWAS[A:D]

Status of Word Alignment. When DEMUX_WAS[A:D] = “1”, word alignment

is achieved for Channel x.

DEMUX_WAS[A:D]= “0” on device reset.

[4]A

[5]B

[6]C

[7]D

CH248_SYNC[A:D]

Status of Channel Alignment. When CH248_SYNC[A:D] = ”1”, multi-channel

alignment is achieved for Channel x.

CH248_SYNC[A:D]= “0” on device reset.

30814

[0:2]

Reserved

[3]A&B

[4]C&

SYNC2[1:2]OOSL

Multi-Channel Out-Of-Sync Status. When SYNC2[1:2] OOS= “1”, dual-chan-

nel synchronization has failed.

SYNC2[1:2] OOS on device reset.

[5]

SYNC4OOS

Multi-Channel Out-Of-Sync Status. When SYNC4_OOS= “1”, quad-channel

synchronization has failed.

SYNC4_OOS= “0” on device reset.

[6:7]

Reserved

SPI4 Core RX Control Registers (Read and Write)

30900 A

30A00 B

[0:7]

RX_CAL_M_MAIN

Number of times calendar sequence is repeated between insertions of fram-

ing pattern (RX SPI4, main)

30901 A

30A01 B

[0:5]

Reserved

[6:7]

RX_CAL_LEN_MAIN 00

Length of calendar sequence on the RX status frame (SPI4, main)

This is the most signiﬁcant 2 bits of 10 total.

30902 A

30A02 B

[0:7]

RX_CAL_LEN_MAIN 00

Length of calendar sequence on the RX status frame (SPI4, main).

This is the least signiﬁcant 8 bits of 10 total

30903 A

30A03 B

[0:7]

RX_CAL_M_SHD

Number of times shadow calendar sequence is repeated between insertions

of framing pattern for the RX side of SPI4.

30904 A

30A04 B

[0:5]

Reserved

[6:7]

RX_CAL_LEN_SHD

Shadow calendar length for the RX status frame of SPI4.

Upper 2 bits.

30905 A

30A05

[0:7]

RX_CAL_LEN_SHD

Shadow calendar length for the RX status frame of SPI4.

Lower 8 bits.

30906 A

30A06 B

[0:1]

RX_DPRAM_0_NUM

FIFO

Number of virtual FIFOs in RX DPRAM bank 0

00 = 1 FIFO

01 = 2 FIFOs

10 = 4 FIFOs

11 = 8 FIFOs

[2:3]

RX_DPRAM_1_NUM

FIFO

Number of virtual FIFOs in RX DPRAM bank 1

[4:5]

RX_DPRAM_2_NUM

FIFO

Number of virtual FIFOs in RX DPRAM bank 2

[6:7]

RX_DPRAM_3_NUM

FIFO

Number of virtual FIFOs in RX DPRAM bank 3

Table 47. Memory Map (Continued)

(0x)

Abso-

lute

Address

Bit

Name

Reset

Value

(0x)

Description

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