ORSPI4 datasheet(164/263 Pages) LATTICE

164 / 263 page

Lattice Semiconductor

ORCA ORSPI4 Data Sheet

164

30917 A

30A17 B

[0:1]

Reserved

[2]

RX_CAL_MEM_SEL 00

Enables calendar memory for SPI4 RX calendar to be written via

MPI. The RX_CAL memory encompasses address ranges 0 to 2047.

Addresses 0 to 1023 are for the main calendar; addresses 1024 to 2047 are

for the shadow calendar. SPI4 RX Calendar memory is write only.

[3]

RX_PDM_MEM_SEL

Enables memory for SPI4 RX port descriptors to be read or written via MPI.

Addresses 0 to 255 valid for this memory.

Each location contains 3 unused bits, 2 BANK_ID bits and 3 PARTITION_ID

bits.

[4]

TX_CAL_MEM_SEL

Enables calendar memory for SPI4 TX calendar to be written via

MPI. The TX_CAL memory encompasses address ranges 0 to 2047.

Addresses 0 to 1023 are for the main calendar; addresses 1024 to 2047 are

for the shadow calendar.SPI4 TX Calendar memory is write only.

[5]

TX_PDM_MEM_SEL

Enables memory for SPI4 TX port descriptors to be read or written via MPI.

The valid address range is 0 to 1023. The least signiﬁcant 2 address bits are

used as byte enables.

00 accesses the PORT_ID (8 bits)

01 accesses PARTITION_ID (3 bits), an unused bit and BURST_VAL (4 bits)

10 accesses 4 unused bits, MB_EN (1 bit), M (1 bit), and BANK_ID (2 bits).

The upper 8 bits of address represent the port number being conﬁgured.

[6]

TX_CRED_MEM_SE

Enables read and write access to TX credits via MPI. The valid memory

address range is 0 to 511. The credit for each port is a 10-bit entity. The

upper 8 of 9 bits of address select which port to read or write. The lowest bit

of address acts as a byte select as follows:

0 accesses the least signiﬁcant 8 bits of the credit ﬁeld

1 accesses the most signiﬁcant 2 bits (right-justiﬁed) of the credit ﬁeld

[7]

TX_STAT_MEM_SEL

Enables memory for SPI4 TX status to be read or written via MPI. This

memory used address ranges 0 to 255. Each location has six left-most bits

unused and two status bits.

30920 A

30A20 B

[0:3}

TX_DPRAM_FULL_T

YPE_SEL

Full level select for all partitions within bank [0:3]. Valid for 32-bit, 64-bit and

128-bit mode.

0 = truly full

1 = 3/4 FIFO lines full +1. E.g.: For a FIFO size of 32, this value will be (3/4 *

32) + 1 = 25 lines. Each line in the FIFO is always 128 bits of data irrespec-

tive of the aggregation mode

[4:7]

RX_DPRAM_EMPTY

_TYPE_SEL

Empty level select for all partitions within bank [0:3]. Valid for 32-bit, 64-bit

and 128-bit mode.

0 = truly empty

1 = 1/4 full - 1. E.g.: For a FIFO size of 32, this value will be (1/4 * 32) - 1 = 7

lines. Each line in the FIFO is always 128 bits of data irrespective of the

aggregation mode

SPI4 Core TX Control Registers (Read and Write)

30921 A

30A21 B

[0:7]

TX_CAL_M_MAIN

Number of times the transmit main calendar sequence is repeated between

insertions of framing pattern.

30922 A

30A22 B

[0:5]

Reserved

[6:7]

TX_CAL_LEN_MAIN 00

Length of main calendar sequence on the TX status frame. These are the

most signiﬁcant 2 bits of 10 total.

30923 A

30A23

[0:7]

TX_CAL_LEN_MAIN

Length of main calendar sequence on the TX status frame. These are the

least signiﬁcant 8 bits of 10 total.

30924 A

30A24 B

[0:7]

TX_CAL_M_SHD

Number of times the transmit shadow calendar sequence is repeated

between insertions of framing pattern.

Table 47. Memory Map (Continued)

(0x)

Abso-

lute

Address

Bit

Name

Reset

Value

(0x)

Description

ORSPI4 датащи(PDF) 164 Page - Lattice Semiconductor

ORSPI4 датащи(HTML) 164 Page - Lattice Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL