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ORSPI4 датащи(PDF) 58 Page - Lattice Semiconductor

номер детали ORSPI4
подробное описание детали  Dual SPI4 Interface and High-Speed SERDES FPSC
PDF  263 Pages
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производитель  LATTICE [Lattice Semiconductor]
домашняя страница  http://www.latticesemi.com
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ORSPI4 датащи(HTML) 58 Page - Lattice Semiconductor

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Lattice Semiconductor
ORCA ORSPI4 Data Sheet
58
• TX_CAL_M_MAIN (address 30921 in SPIA and 30A21 in SPIB) is set to the number of times the calendar
sequence needs to be repeated between framing patterns.
• The shadow calendar can be programmed in the same identical fashion as the main calendar using the steps
described above.
To enable hitless switching between main and shadow calendar memories, the TX_CAL_SW_EN bit (address
30916 in SPIA and 30A16 in SPIB) should be set to ‘1’. This will cause the transmit status logic to detect the calen-
dar select word after the framing pattern. A “01” detected on the calendar select word selects the main calendar. A
“10” on the calendar select word selects the shadow calendar. It is important to enable this feature in the receive
device on the other end of the SPI4 link. If the receive device is a Lattice ORSPI4 device, this is done by setting
RX_CAL_SW_EN bit (address 30916 in SPIA and 30A16 in SPIB) to ‘1’. This will cause the far-end receive status
logic to insert the calendar select word after the framing pattern.
Table 11. Transmit Calendar Memory Contents
MIN_BURST_MODE
The number of transmitted data bytes in a given port’s SPI-4 data segment can be programmed by setting the
BURST_VAL for a given port in the Port Descriptor Memory. In general, setting a port’s BURST_VAL will result in
transmitted data segments of length (16 * BURST_VAL) bytes. However, data segments shorter than (16 *
BURST_VAL) bytes will occur about 15% of the time. There are three reasons for shorter data segments:
1. End-of-packet (EOP) causes segment to terminate
2. Insufficient data is written into a port’s transmit FIFO to support a full data burst.
3. ORSPI4 core logic causes occasional short segments.
Reason 1 will always naturally occur with any SPI4 link and so can never be completely eliminated. However, the
following steps which take advantage of the MIN_BURST_MODE will eliminate short data segments caused by
reasons 2 and 3:
1. Set MIN_BURST_MODE (address 30916, bit 3 for SPIA and 30A16, bit 3 for SPIB) to 1.
TX Calendar Memory
Address
TX Calendar Memory
Contents (Port ID)
Port Number
0x00
0x00
A1
0x01
0x01
A2
0x02
0x02
A3
0x03
0x03
B1
0x04
0x00
A1
0x05
0x01
A2
0x06
0x02
A3
0x07
0x04
B2
0x08
0x00
A1
0x09
0x01
A2
0x0a
0x02
A3
0x0b
0x05
B3
0x0c
0x00
A1
0x0d
0x01
A2
0x0e
0x02
A3
0x0f
0x06
B4



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