ORSPI4 datasheet(166/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

166

30941 A

30A41 B

[0:7]

TX_ALPHA (byte a)

Number of times training sequence needs to be repeated every

TX_DATA_MAX_T cycles. The number is formed from 2 TX_ALPHA bytes,

in the order {a,b}.

30942 A

30A42 B

[0:7]

TX_ALPHA (byte b)

Number of times training sequence needs to be repeated every

TX_DATA_MAX_T cycles. The number is formed from 2 TX_ALPHA bytes,

in the order {a,b}.

30943 A

30A43 B

[0:3]

TX_DPRAM_FIFO_O

VERRUN_INT_EN

These bits act as enables for the status ﬂags and the interrupts regarding an

overrun of the 4 TX DPRAM FIFO banks.

[4:7]

TX_DPRAM_FIFO_U

RRUN_INT_EN

These bits act as enables for the status ﬂags and the interrupts regarding an

underrun of the 4 TX DPRAM FIFO banks.

30944 A

30A44 B

[0:4]

Reserved

[5:7]

TX_DIP2_ERR_TH

Number of consecutive bad/good DIP-2 code words for SPI4 TX to lose/gain

alignment. Loss of alignment is indicated by TX_STATUS_LOF_STS

30945 A

30A45 B

[0:2]

TX_FIFO_THRESHO

LD_L

Low watermark threshold for sync input FIFO within TDP. This is used only if

MIN_BURST_MODE is set. Depending on the number of lines in a burst,

this threshold should be set to integer[(BURST_VAL/4) + 1]

[3:7]

TX_FIFO_THRESHO

LD_H

High watermark threshold for async FIFO within TDP to declare a full condi-

tion. This causes writes to the TDP to be held off; meaning that an overrun

condition can not occur here.

SPI4 Core RX/TX Spare Controls (Read and Write)

30946 A

30A46 B

[0:7]

Reserved

30908 A

30A08 B

[0:7]

Reserved

SPI4 Core Status Registers (Read Only)

30909 A

30A09 B

[0:7]

Reserved

3090A A

30A0A B

[0:7]

RX_DIP4_ERR_CNT 00

Count of DIP4 errors. Count will reset to “0” on a read of this register. If

count reaches maximum (255) it will hold.

3090B A

30A0B B

[0:7]

TX_DIP2_ERR_CNT 00

Count of status framing errors. See SIP2_ERR_STS. Count will reset to “0”

after a read of this register. If count reaches maximum (255) it will hold.

3090C A

30A0C B

[0:7]

RX_DPRAM_0_FIFO

_OVERRUN_STS

Overrun status of bank 0 DPRAM FIFOs 0 to 7. These are enabled by

RX_DPRAM_FIFO_OVERRUN_INT_EN[0] (register 30912[A], 30A12[B]).

These bits clear when read, but will set immediately if the error condition

persists.

3090D A

30A0D B

[0:7]

RX_DPRAM_1_FIFO

_OVERRUN_STS

Overrun status of bank 1 DPRAM FIFOs 0 to 7. These are enabled by

RX_DPRAM_FIFO_OVERRUN_INT_EN[1] (register 30912[A], 30A12[B]).

These bits clear when read, but will set immediately if the error condition

persists.

3090E A

30A0E B

[0:7]

RX_DPRAM_2_FIFO

_OVERRUN_STS

Overrun status of bank 2 DPRAM FIFOs 0 to 7. These are enabled by

RX_DPRAM_FIFO_OVERRUN_INT_EN[2] (register 30912[A], 30A12[B]).

These bits clear when read, but will set immediately if the error condition

persists.

3090F A

30A0F B

[0:7]

RX_DPRAM_3_FIFO

_OVERRUN_STS

Overrun status of bank 3 DPRAM FIFOs 0 to 7. These are enabled by

RX_DPRAM_FIFO_OVERRUN_INT_EN[3] (register 30912[A], 30A12[B]).

These bits clear when read, but will set immediately if the error condition

persists.

30918 A

30A18 B

[0:7]

RX_DPRAM_0_FIFO

_URRUN_STS

Underrun status of bank 0 DPRAM FIFOs 0 to 7. These are enabled by

RX_DPRAM_FIFO_URRUN_INT_EN[0] (register 30912[A], 30A12[B]).

These bits clear when read, but will set immediately if the condition persists.

Table 47. Memory Map (Continued)

(0x)

Abso-

lute

Address

Bit

Name

Reset

Value

(0x)

Description

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