ORSPI4 datasheet(160/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

160

30821

[0]

NOCHALGN

Bypass channel alignment. NOCHALGN =1 causes bypassing of multi-

channel alignment FIFOs for the corresponding SERDES quad.

NOCHALGN = “0” on device reset.

[1:3]

Reserved

[4:5]

RCKSEL[0:1]

Source for RCK78 (00=A, 10=B, 01=C, 11=D)

[6:7]

TCKSEL[0:1]

Source for TCK78 (00=A, 10=B, 01=C, 11=D)

30830

[0:3]

Reserved

[4]

SCHAR_ENA

Set this to 1 to enable characterization mode for the SERDES. Character-

ization mode also requires inputs TESTMD[1:0]N=00, and FPGA interface

pin, ENABLE_SPI4_B = “0”.

The outputs for the SERDES can be observed at the following ports:

TBC311

→ PMID20

→ PMID21

BYTSYNC

→ PMID22

WDSYNC

→ PMID23

RBCO

→ PMID24

RBC1

→ PMID25

LDOUT9

→ PMID26

LDOUT8

→ PMID 27

LDOUT7

→ PMID28

LDOUT6

→ PMID29

LDOUT5

→ PMID30

LDOUT4

→ PMID31

LDOUT3

→ PMID32

LDOUT2

→ PMID33

LDOUT1

→ PMID34

LDOUT0

→ PMID35

[5]

SCHAR_TXSEL

Set this to 1 to enable driving of low speed TX ports of the SERDES during

characterization mode. The inputs used During this mode are:

TBC

← PMIA15

LDIN9

← PMIA14

LDIN8

← PMIA13

LDIN7

← PMIA11

LDIN6

← PMIA9

LDIN5

← PMAI8

LDIN4

← PMIA7

LDIN3

← PMIA6

LDIN2

← PMIA5

LDIN1

← PMIA4

LDIN0

← PMIA2

[6:7]

SCHAR_CHAN

Selects the channel to observe and control during SERDES characterization

mode:

00 = A

01 = B

10 = C

11 = D

Status Registers (Read Only), x = [A, ...,D]

30804

[0:1]A

[2:3]B

[4:5]C

[6:7]D

XAUISTAT[A:D][0:1]

XAUI Status Register. Status of XAUI link state machine for Channel x

00—No synchronization.

01—No comma (see XAUI state machine) and at least 1 cell value detected

10—Synchronization done.

11—Not used.

XAUISTAT_x[0:1] = 00 on device reset.

Table 47. Memory Map (Continued)

(0x)

Abso-

lute

Address

Bit

Name

Reset

Value

(0x)

Description

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