ORSPI4 datasheet(158/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

158

SERDES Common Transmit and Receive Channel Conﬁguration Registers (Read/Write), x = [A, ...,D]

30004

30014

30024

30034

[0]

Reserved

Reserved. Must be set to “0”

Set to “0” on device reset.

[1]

MASK_x

Transmit and Receive Alarm Mask Bit, Channel x. When MASK_x = “1”, the

transmit and receive alarms of a channel are prevented from generating an

interrupt (i.e., they are masked or disabled). The MASK_x bit overrides the

individual alarm mask bits in the Alarm Mask Registers.

MASK_x = “1” on device reset.

[2]

SWRST_x

Transmit and Receive Software Reset Bit, Channel x. When SWRST_x =

“1”, this bit provides the same function as the hardware reset, except that all

conﬁguration register settings are unaltered. This is not a self-clearing bit.

Once set, this bit must be manually set and cleared.

SWRST_x = “0” on device reset.

[3:6]

Reserved

[7]

TESTEN_x

Transmit and Receive Test Enable Bit, Channel x. When TESTEN_x = “1”,

the transmit and receive sections are placed in test mode. The Test-

Mode[4:0] bits in the Global Control Registers specify the particular test,

and must also be set.

NOTE: When the global test enable bit GTESTEN = “0”, the individual chan-

nel test enable bits are used to selectively place a channel in test or normal

mode. When GTESTEN = “1”, all channels are set to test mode regardless

of their TESTEN setting

TESTEN_x = “0” on device reset.

SERDES Global Control Registers (Read/Write) Acts on all four Channels in SERDES Quad A or SERDES Quad B.

30005

[0]

Reserved

Set to “0” on device reset.

[1]

GMASK

Global Mask. When GMASK = “1”, the transmit and receive alarms of all

channel in the SERDES quad are prevented from generating an interrupt

(i.e., they are masked or disabled). The GMASK bit overrides the individual

MASK_x bits. GMASK = “1” on device reset.

[2]

GSWRST

Software reset bit. The GSWRST bit provides the same function as the

hardware reset for the transmit and receive sections of all four channels,

except that the device conﬁguration settings are not affected when

GSWRST is asserted. This is not a self-clearing bit. Once set, this bit must

be manually set and cleared. The GSWRST bit overrides the individual

SWRST_x bits.

GSWRST = “0” on device reset.

[3]

GPWRDNT

Powerdown Transmit Function. When GPWRDNT = “1”, sections of the

transmit hardware for all four channels of are powered down to conserve

power. The GPWRDNT bit overrides the individual PWRDNT_x bits.

GPWRDNT= “0” on device reset.

[4]

GPWRDNR

Powerdown Receive Function. When GPWRDNR = “1”, sections of the

receive hardware for all four channels are powered down to conserve power.

The GPWRDNR bit overrides the individual PWRDNR_x bits.

GPWRDNR = “0” on device reset.

[5]

Reserved

Reserved, “1” on device reset.

[6]

Reserved

[7]

GTESTEN

Test Enable Control. When GTESTEN = “1”, the transmit and receive sec-

tions of all four channels are placed in test mode. The GTESTEN bit over-

rides the individual TESTEN_x bits. GTESTEN = “0” on device reset.

30006

[0:4]

TestMode

TestMode - See Test Mode section for settings

[5:7]

Reserved

Table 47. Memory Map (Continued)

(0x)

Abso-

lute

Address

Bit

Name

Reset

Value

(0x)

Description

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