ORSPI4 datasheet(159/263 Pages) LATTICE

159 / 263 page

Lattice Semiconductor

ORCA ORSPI4 Data Sheet

159

Control Registers (Read/Write), x = [A, ...,D]

30800

[0]A

[1]B

[2]C

[3]D

ENBYSYNC[A:D]

ENBYSYNC[A:D] = “1” Enables Receiver Byte Synchronization for Channel

ENBYSYNC[A:D] = “0” on device reset.

[4]A

[5]B

[6]C

[7][D]

LCKREFN[A:D]

LCKREFN[A:D]= “0” Locks the receiver PLL to ref reference clock for Chan-

nel x.

LCKREFN[A:D]= “1” = Locks the receiver to data for Channel x.

NOTE: When LCKREFN[A:D] = “0”, the corresponding LKI_x bit is also zero.

LCKREFN[A:D]= “0” on device reset.

30801

[0]A

[1]B

[2]C

[3]D

LOOPENB[A:D]

Enable Loopback Mode for Channel x. When LOOPEN[A:D]= “1”, the trans-

mitter high-speed output is looped back to the receiver high-speed input.

This mode is similar to high-speed loopback mode enabled by TEST-

MODE[A:D] except that LOOPEN[A:D] disables the high-speed serial out-

put.

LOOPEN[A:D]= “0” on device reset.

[4]A

[5]B

[6]C

[7]D

NOWDALIGN[A:D]

Word Align Disable Bit. When NOWDALIGN[A:D]= “1”, receiver word align-

ment is disabled for Channel x.

NOWDALIGN[A:D]= “0” on device reset.

30810

[0]A

[1]B

[2]C

[3]D

DOWDALIGN[A:D]

Word Realign Bit. When DOWDALIGN[A:D] transitions from “0” to “1”, the

receiver realigns on the next comma character for Channel x.

DOWDALIGN[A:D]= “0” on device reset.

[4]A

[5]B

[6]C

[7]D

FMPU_STR_EN[A:D]

Enable multi-channel alignment for Channel x. When

FMPU_STR_EN[A:D]= “1”, the corresponding channel participates in multi-

channel alignment.

FMPU_STR_EN[A:D]= “0” on device reset.

30811

[0:1]A

[2:3]B

[4:5]C

[6:7]D

FMPU_SYNMODE[A:

D][0:1]

Sync mode for x

00 = No channel alignment

10 = Twin channel alignment

01 = Quad channel alignment

30820

[0]A

[1]B

[2]C

[3]D

FMPU_RESYNC1[A:

Resync a Single Channel. When FMPU_RESYNC1[A:D] transitions from “0”

to “1”, the corresponding channel is resynchronized (the write and read

pointers are reset).

FMPU_RESYNC1[A:D]=”0” on device reset.

[4]A &

[5]C

FMPU_RESYNC2[1:

Resync a Pair of Channels. When FMPU_RESYNC2[1:2] transitions from a

“0” to a “1”, the corresponding channel pair is resynchronized.

FFMPU_RESYNC2[1:2]= “0” on device reset.

[6]

FMPU_RESYNC4[1:

Resync a Four-Channel Group. When FMPU_RESYNC4 transitions from a

“0” to a “1”, the corresponding four-channel group is resynchronized.

FMPU_RESYNC4= “0” on device reset.

[7]

XAUI_MODE

Controls use of XAUI link state machine in place of Fibre-Channel state

machine. When XAUI_MODE= “1”, all four channels in the SERDES quad

enable their XAUI link state machines. (LINKSM_x bits are ignored).

XAUI_MODE= “0” on device reset.

Table 47. Memory Map (Continued)

(0x)

Abso-

lute

Address

Bit

Name

Reset

Value

(0x)

Description

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