ORSPI4 datasheet(157/263 Pages) LATTICE

157 / 263 page

Lattice Semiconductor

ORCA ORSPI4 Data Sheet

157

SERDES Alarm Mask Registers (Read/Write), x = [A, ...,D]

30001

30011

30021

30031

[0]

Reserved

Reserved. Must be set to “1”.

Set to “1” on device reset.

[1]

MLKI_x

Mask Receive PLL Lock Indication, Channel x.

[2:7]

Reserved

SERDES Common Transmit and Receive Channel Conﬁguration Registers (Read/Write), x = [A, ...,D]

30002

30012

30022

30032

[0]

TXHR_x

Transmit Half Rate Selection Bit, Channel x.

When TXHR_x = “1”, HDOUT_x's baud rate = (REFCLK*10) and TCK78

=(REFCLK/4); when TXHR_x=0, HDOUT_x's baud rate = (REFCLK*20) and

TCK78=(REFCLK[A:B]/2).

TXHR_x = 0 on device reset.

[1]

PWRDNT_x

Transmit Powerdown Control Bit, Channel x. When PWRDNT_x = “1”, sec-

tions of the transmit hardware are powered down to conserve power.

PWRDNT_x = 0 on device reset.

[2]

PE0_x

Transmit Preemphasis Selection Bit 0, Channel x. PE0_x and PE1_x select

one of three preemphasis settings for the transmit section.

PEO_x=PE1_x = 0, Preemphasis is 0%

PEO_x=1, PE1_x = 0 or PEO_x=0, PE1_x = 1, Preemphasis is 12.5%

PEO_x=PE1_x = 1, Preemphasis is 25%.

PEO_x=PE1_x = 0 on device reset.

[3]

PE1_x

[4]

HAMP_x

Transmit Half Amplitude Selection Bit, Channel x. When HAMP_x = “1”, the

transmit output buffer voltage swing is limited to half its normal amplitude.

Otherwise, the transmit output buffer maintains its full voltage swing.

HAMP_x = 0 on device reset.

[5]

Reserved

Reserved. Must be set to 0

Set to “0” on device reset.

[6]

Reserved

[7]

8b10bT_x

Transmit 8b/10b Encoder Enable Bit, Channel x. When 8b10bT_x = “1”, the

8b/10b encoder in the transmit path is enabled. Otherwise, the data is

passed unencoded.

8b10bT_x = “0” on device reset.

30003

30013

30023

30033

[0]

RXHR_x

Receive Half Rate Selection Bit, Channel x.

When RXHR_x =”1”, HDIN_x's baud rate = (REFCLK*10) and

RCK78=(REFCLK/4); when RXHR_x= “0”, HDIN_x's baud rate = (REF-

CLK*20) and RCK78=(REFCLK/2).

RXHR_x = “0” on device reset.

[1]

PWRDNR_x

Receiver Power Down Control Bit, Channel x. When PWRDNR_x = 1, sec-

tions of the receive hardware are powered down to conserve power.

PWRDNR_x = “0” on device reset.

[2]

Reserved

Reserved. Must be set to “1”.

Set to “1” on device reset.

[3]

8b10bR_x

Receive 8b/10b Decoder Enable Bit, Channel x. When 8b10bR = “1”, the

8b/10b decoder in the receive path is enabled. Otherwise, the data is

passed undeocded.

8b10bR_x = “0” on device reset.

[4]

LINKSM_x

Link State Machine Enable Bit, Channel x. When LINKSM_x = “1”, the

receiver Fiber Channel link state machine is enabled. Otherwise, the Fibre

Channel link state machine is disabled.

NOTE: LINKSM_x is ignored when XAUI_MODE_x= “1”.

LINKSM_x = “0” on device reset.

[5:7]

Reserved

Table 47. Memory Map (Continued)

(0x)

Abso-

lute

Address

Bit

Name

Reset

Value

(0x)

Description

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