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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PSD813F1 датащи(PDF) 35 Page - STMicroelectronics |
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PSD813F1 датащи(HTML) 35 Page - STMicroelectronics |
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35 / 120 page  Preliminary PSD813F1-A 31 The PSD813F1 Functional Blocks (cont.) FLASH DPLD EEPROM SRAM RS0 EES0-3 FS0-7 CS CS CS OE OE RD PSEN OE Figure 8. 8031 Memory Modes – Separate Space Mode FLASH DPLD EEPROM SRAM RS0 EES0-3 FS0-7 RD CS CS CS RD OE OE VM REG BIT 2 PSEN VM REG BIT 0 VM REG BIT 1 VM REG BIT 3 VM REG BIT 4 OE Figure 9. 80C31 Memory Mode – Combined Space Mode 9.1.3.2 Configuration Modes for MCUs with Separate Program and Data Spaces 9.1.3.2.1 Separate Space Modes Code memory space is separated from data memory space. For example, the PSEN signal is used to access the program code from the Flash Memory, while the RD signal is used to access data from the EEPROM, SRAM and I/O Ports. This configuration requires the VM register to be set to 0Ch. 9.1.3.2.2 . Combined Space Modes The program and data memory spaces are combined into one space that allows the main Flash Memory, EEPROM, and SRAM to be accessed by either PSEN or RD. For example, to configure the main Flash memory in combined space mode, bits 2 and 4 of the VM register are set to “1”. 9.1.3.3 80C31 Memory Map Example See Application Notes 57 and 64 for examples. |
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