PSD813F1 datasheet(77/120 Pages) STMICROELECTRONICS

77 / 120 page

Preliminary

PSD813F1-A

Port C Pin

JTAG Signals

Description

PC0

TMS

Mode Select

PC1

TCK

Clock

PC3

TSTAT

Status

PC4

TERR

Error Flag

PC5

TDI

Serial Data In

PC6

TDO

Serial Data Out

Table 34. JTAG Port Signals

The

PSD813F1

Functional

Blocks

(cont.)

9.6 Programming In-Circuit using the JTAG Interface

The JTAG interface on the PSD813F1 can be enabled on Port C (see Table 34). All memory

(Flash and EEPROM), PLD logic, and PSD configuration bits may be programmed through

the JTAG interface. A blank part can be mounted on a printed circuit board and

programmed using JTAG.

The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional

signals, TSTAT and TERR, are optional JTAG extensions used to speed up program and

erase operations.

By default, on a blank PSD (as shipped from factory or after erasure), four pins on Port C

are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO.

See Application Note 54 for more details on JTAG In-System-Programming.

*SR_cod and Periph Mode bits in the VM Register are always cleared to zero on power on or warm reset.

Port Configuration

Power On Reset

Warm Reset

Power Down Mode

MCU I/O

Input Mode

Unchanged

PLD Output

Valid after internal

Valid

Depend on inputs to

PSD configuration

PLD (address are

bits are loaded

blocked in PD mode)

Address Out

Tri-stated

Not defined

Data Port

Tri-stated

Peripheral I/O

Tri-stated

Table 33. Status During Power On Reset, Warm Reset and Power Down Mode

Power On Reset

Warm Reset

Power Down Mode

PMMR0, 2

Cleared to “0”

Unchanged

Micro

⇔Cells Flip

Cleared to “0” by

Depend on .re and

Flop status

internal power on

.pr equations

reset

VM Register*

Initialized based on

Unchanged

the selection in

PSDsoft

Configuration Menu.

Configuration Menu

All other registers

Cleared to “0”

Unchanged

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