PSD813F1 datasheet(62/120 Pages) STMICROELECTRONICS

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PSD813F1-A

Preliminary

The

PSD813F1

Functional

Blocks

(cont.)

9.4.3.1 Control Register

Any bit set to ‘0’ in the Control Register sets the corresponding Port pin to MCU I/O Mode,

and a ‘1’ sets it to Address Out Mode. The default mode is MCU I/O. Only Ports A and B

have an associated Control Register.

9.4.3.2 Direction Register

The Direction Register, in conjunction with the output enable (except for Port D), controls

the direction of data flow in the I/O Ports. Any bit set to ‘1’ in the Direction Register will

cause the corresponding pin to be an output, and any bit set to ‘0’ will cause it to be an

input. The default mode for all port pins is input.

Figures 26 and 28 show the Port Architecture diagrams for Ports A/B and C, respectively.

The direction of data flow for Ports A, B, and C are controlled not only by the direction

enable product term is not active, the Direction Register has sole control of a given pin’s

direction.

An example of a configuration for a port with the three least significant bits set to output and

the remainder set to input is shown in Table 26. Since Port D only contains three pins, the

Direction Register for Port D has only the three least significant bits active.

Direction Register Bit

Port Pin Mode

Input

Output

Table 24. Port Pin Direction Control,

Output Enable P.T. Not Defined

Direction Register Bit

Output Enable P.T.

Port Pin Mode

Input

Output

Table 25. Port Pin Direction Control, Output Enable P.T. Defined

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

000

Table 26. Port Direction Assignment Example

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