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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PSD813F1 датащи(PDF) 65 Page - STMicroelectronics |
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PSD813F1 датащи(HTML) 65 Page - STMicroelectronics |
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65 / 120 page  Preliminary PSD813F1-A 61 The PSD813F1 Functional Blocks (cont.) 9.4.5 Ports A and B – Functionality and Structure Ports A and B have similar functionality and structure, as shown in Figure 26. The two ports can be configured to perform one or more of the following functions: t MCU I/O Mode t CPLD Output – Micro ⇔Cells McellAB[7:0] can be connected to Port A or Port B. McellBC[7:0] can be connected to Port B or Port C. t CPLD Input – Via the input Micro ⇔Cells. t Latched Address output – Provide latched address output per Table 30. t Address In – Additional high address inputs using the Input Micro ⇔Cells. t Open Drain/Slew Rate – pins PA[3:0] and PB[3:0] can be configured to fast slew rate, pins PA[7:4] and PB[7:4] can be configured to Open Drain Mode. t Data Port – Port A to D[7:0] for 8 bit non-multiplexed bus t Multiplexed Address/Data port for certain types of microcontroller interfaces. t Peripheral Mode – Port A only |
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