PSD813F1 datasheet(19/120 Pages) STMICROELECTRONICS

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Preliminary

PSD813F1-A

9.0

The

PSD813F1

Functional

Blocks

As shown in Figure 1, the PSD813F1 consists of six major types of functional blocks:

t Memory Blocks

t PLD Blocks

t Bus Interface

t I/O Ports

t Power Management Unit

t JTAG Interface

The functions of each block are described in the following sections. Many of the blocks

perform multiple functions, and are user configurable.

9.1 Memory Blocks

The PSD813F1 has the following memory blocks:

• The main Flash memory

• Secondary EEPROM memory

• SRAM.

The memory select signals for these blocks originate from the Decode PLD (DPLD) and

are user-defined in PSDsoft.

Table 8 summarizes the PSD813F1 memory blocks.

Device

Main Flash

EEPROM

SRAM

PSD813F1

128KB

32KB

2KB

Table 8. Memory Blocks

9.1.1 Main Flash and Secondary EEPROM

The 1 Mbit main Flash memory block is divided evenly into eight 16 Kbyte sectors. The

EEPROM memory is divided into four sectors of eight Kbytes each. Each sector of either

memory can be separately protected from program and erase operations.

Flash memory may be erased on a sector-by-sector basis and programmed byte-by-byte.

Flash sector erasure may be suspended while data is read from other sectors of memory

and then resumed after reading.

EEPROM may be programmed byte-by-byte or sector-by-sector, and erasing is automatic

and transparent. The integrity of the data can be secured with the help of Software Data

Protection (SDP). Any write operation to the EEPROM is inhibited during the first five

milliseconds following power-up.

During a program or erase of Flash, or during a write of the EEPROM, the status can be

output on the Rdy/Bsy pin of Port C3. This pin is set up using PSDsoft Configuration.

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