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PSD813F1 датащи(PDF) 97 Page - STMicroelectronics

номер детали PSD813F1
подробное описание детали  Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PDF  120 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD813F1 датащи(HTML) 97 Page - STMicroelectronics

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Preliminary
PSD813F1-A
93
-15
-20
PT
TURBO
Slew
Symbol
Parameter
Conditions
Min
Max
Min
Max
Aloc
OFF
*
Rate
Unit
Maximum Frequency
External Feedback
1/(tSA+t COA)
19.2
16.9
MHz
Maximum Frequency
fMAXA
Internal Feedback ( fCNTA)
1/(tSA+t COA–10)
23.8
20.4
MHz
Maximum Frequency
Pipelined Data
1/(tCH A+t CLA)
27
24.4
MHz
tSA
Input Setup Time
12
13
Add 4 Add 20
ns
tHA
Input Hold Time
15
17
ns
tCHA
Clock High Time
22
25
Add 20
ns
tCLA
Clock Low Time
15
16
Add 20
ns
tCOA
Clock to Output Delay
40
46
Add 20 Sub 6
ns
tARD
CPLD Array Delay
Any Micro
⇔Cell
29
33
Add 4
ns
tMINA
Minimum Clock Period
1/ fCNTA
42
49
ns
CPLD Micro
⇔Cell Asynchronous Clock Mode Timing (3.0 V to 3.6 V Versions)
NOTE: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX.
*ZPSD Versions Only.
-15
-20
PT
TURBO
Symbol
Parameter
Conditions
Min
Max
Min
Max
Aloc
OFF
*
Unit
tIS
Input Setup Time
(Note 1)
0
0
ns
tIH
Input Hold Time
(Note 1)
25
30
Add 20
ns
tINH
NIB Input High Time
(Note 1)
13
15
ns
tINL
NIB Input Low Time
(Note 1)
13
15
ns
tINO
NIB Input to Combinatorial
Delay
(Note 1)
62
70
Add 4
Add 20
ns
Input Micro
⇔Cell Timing (3.0 V to 3.6 V Versions)
PSD813F1V AC/DC Parameters – CPLD Timing Parameters
(3.0 V to 3.6 V Versions)
*ZPSD Versions Only.



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