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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PSD813F1 датащи(PDF) 96 Page - STMicroelectronics |
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PSD813F1 датащи(HTML) 96 Page - STMicroelectronics |
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96 / 120 page  PSD813F1-A Preliminary 92 PSD813F1V AC/DC Parameters – CPLD Timing Parameters (3.0 V to 3.6 V Versions) -15 -20 Slew PT TURBO Rate Symbol Parameter Conditions Min Max Min Max Aloc OFF * (Note 1) Unit CPLD Input Pin/Feedback to tPD CPLD Combinatorial Output 48 55 Add 4 Add 20 Sub 6 ns tEA CPLD Input to CPLD Output Enable 43 50 Add 20 Sub 6 ns tER CPLD Input to CPLD Output Disable 43 50 Add 20 Sub 6 ns tARP CPLD Register Clear or Preset Delay 48 55 Add 20 Sub 6 ns tARPW CPLD Register Clear or 30 35 Add 20 ns Preset Pulse Width tARD CPLD Array Delay Any Micro ⇔Cell 29 33 Add 4 ns CPLD Combinatorial Timing (3.0 V to 3.6 V Versions) -15 -20 Slew PT TURBO Rate Symbol Parameter Conditions Min Max Min Max Aloc OFF * (Note 1) Unit Maximum Frequency External Feedback 1/(tS +t CO) 17.8 14.7 MHz Maximum Frequency fMAX Internal Feedback ( fCNT) 1/(tS +t CO–10) 19.6 17.2 MHz Maximum Frequency Pipelined Data 1/(tCH +t CL) 33.3 31.2 MHz tS Input Setup Time 27 35 Add 4 Add 20 ns tH Input Hold Time 0 0 ns tCH Clock High Time Clock Input 15 16 ns tCL Clock Low Time Clock Input 15 16 ns tCO Clock to Output Delay Clock Input 35 39 Sub 6 ns tARD CPLD Array Delay Any Micro ⇔Cell 29 33 Add 4 ns tMIN Minimum Clock Period tCH +t CL(Note 2) 29 32 ns CPLD Micro ⇔Cell Synchronous Clock Mode Timing (3.0 V to 3.6 V Versions) NOTES: 1. Fast Slew Rate output available on PA[3:0], PB[3:0], and PD[2:0]. 2. CLKIN tCLCL = tCH + tCL. *ZPSD versions only. NOTE: 1. Fast Slew Rate output available on PA[3:0], PB[3:0], and PD[2:0]. *ZPSD versions only. |
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