DS-AT25DF256-035 Rev.G

Page 22

2024-01-08

© 2024 Renesas Electronics

AT25DF256 Datasheet

11. Status Register Commands

11.1 Read Status Register

The Status Register can be read to determine the device’s ready/busy status, as well as the status of many other

functions such as Hardware Locking and Block Protection. The Status Register can be read at any time, including

during an internally self-timed program or erase operation.The Status Register consists of two bytes.

To read the Status Register, the CS pin must first be asserted and the opcode of 05h must be clocked into the

device. After the opcode has been clocked in, the device begins outputting Status Register data on the SO pin

during every subsequent clock cycle. After the last bit (bit 0) of Status Register Byte 1 has been clocked out, the

first bit (bit 7) of Status Register Byte 2 is clocked out. After the last bit (bit 0) of Status Register Byte 2 has been

clocked out, the sequence repeats itself, starting again with bit 7 of Status Register Byte 1, as long as the CS pin

remains asserted and the clock pin is being pulsed. The data in the Status Register is constantly being updated,

so each repeating sequence outputs new data.

Deasserting the CS pin stops the Read Status Register operation and puts the SO pin into a high-impedance

state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.

1. Only bits 7 and 2 of the Status Register can be modified when using the Write Status Register command.

2. R/W = Readable and writable; R = Readable only.

11.1.1

BPL Bit

The BPL bit is used to control whether the Block Protection (BP0) bit can be modified or not. When the BPL bit is

in the logical 1 state and the WP pin is asserted, the BP0 bit is locked and cannot be modified. The memory array

is locked in the current protected or unprotected state.

When the BPL bit is in the logical 0 state, the BP0 bit is unlocked and can be modified. The BPL bit defaults to the

logical 0 state after device power-up.

The BPL bit can be modified freely whenever the WP pin is deasserted. However, if the WP pin is asserted, then

the BPL bit can only be changed from a logical 0 (BP0 bit unlocked) to a logical 1 (BP0 bit locked). In order to

reset the BPL bit to a logical 0 using the Write Status Register command, the WP pin first must be deasserted.

The BPL and BP0 bits are the only bits of the Status Register that can be user modified via the Write Status

Register command.

Table 6. Status Register Format

Bit 1

Name

Type 2

Description

7

BPL

Block Protection Locked

R/W

0

BP0 bit unlocked (default).

1

BP0 bit locked in current state when WP asserted.

6

RES

Reserved for future use

R

0

Reserved for future use.

5

EPE

Erase/Program Error

R

0

Erase or program operation was successful.

1

Erase or program error detected.

4

WPP

Write Protect (WP) Pin Status

R

0WP is asserted.

1WP is deasserted.

3

RES

Reserved for future use

R

0

Reserved for future use.

2

BP0

Block Protection

R/W

0

Entire memory array is unprotected.

1

Entire memory array is protected.

1

WEL

Write Enable Latch Status

R

0

Device is not write enabled (default).

1

Device is write enabled.

0RDY/BSY

Ready/Busy Status

R

0

Device is ready.

1

Device is busy with an internal operation.