AT25DF256 datasheet(7/47 Pages) RENESAS

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DS-AT25DF256-035 Rev.G

Page 7

2024-01-08

AT25DF256 Datasheet

Pin Descriptions and Pinouts

Table 1. Pin Descriptions

Symbol

Name and Function

Asserted

State

Type

CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the

device is deselected and normally placed in standby mode (not Deep Power-Down mode), and

the SO pin is in a high-impedance state. When the device is deselected, data are not accepted

on the SI pin.

A high-to-low transition on the CS pin is required to start an operation, and a low-to-high

transition is required to end an operation. When ending an internally self-timed operation such as

a program or erase cycle, the device does not enter the standby mode until the completion of the

operation.

Low

Input

SCK

SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow

of data to and from the device. Command, address, and input data present on the SI pin is

always latched in on the rising edge of SCK, while output data on the SO pin is always clocked

out on the falling edge of SCK.

Input

SI (I/O0)

SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data

input including command and address sequences. Data on the SI pin is always latched in on the

rising edge of SCK.

With the Dual-Output Read commands, the SI Pin becomes an output pin (I/O0) in conjunction

with other pins to allow two bits of data on (I/O1-0) to be clocked out on every falling edge of SCK.

To maintain consistency with the SPI nomenclature, the SI (I/O0) pin is referenced as the SI pin

unless specifically addressing the Dual-I/O modes, in which case it is referenced as I/O0.

Data present on the SI pin are ignored whenever the device is deselected (CS is deasserted).

Input/

Output

SO (I/O1) SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin is

always clocked out on the falling edge of SCK.

With the Dual-Output Read commands, the SO Pin remains an output pin (I/O1) in conjunction

with other pins to allow two bits of data on (I/O1-0) to be clocked out on every falling edge of SCK.

To maintain consistency with the SPI nomenclature, the SO (I/O1) pin is referenced as the SO pin

unless specifically addressing the Dual-I/O modes, in which case it is referenced as I/O1. The SO

pin is in the high-impedance state whenever the device is deselected (CS is deasserted).

Input/

Output

WRITE PROTECT: The WP pin controls the hardware locking feature of the device. See Section

9, Protection Commands and Features, for more details on protection features and the WP pin.

The WP pin is internally pulled-high and can be left floating if hardware controlled protection is

not used. However, it is recommended that the WP pin also be externally connected to VCC

whenever possible.

Low

Input

HOLD

HOLD: The HOLD pin is used to temporarily pause serial communication without deselecting or

resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the

SI pin are ignored, and the SO pin is in a high-impedance state.

The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold

condition to start. A Hold condition pauses serial communication only and does not have an

effect on internally self-timed operations such as a program or erase cycle. See Section 12.7 for

additional details on the Hold operation.

The HOLD pin is internally pulled-high and can be left floating if the Hold function is not used.

However, it is recommended that the HOLD pin also be externally connected to VCC whenever

possible.

Low

Input

VCC

DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to the device.

Operations at invalid VCC voltages can produce spurious results; do not attempt this.

Power

GND

GROUND: The ground reference for the power supply. Connect GND to the system ground.

Power

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