AT25DF256 datasheet(36/47 Pages) RENESAS

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DS-AT25DF256-035 Rev.G

Page 36

2024-01-08

AT25DF256 Datasheet

13.4 AC Characteristics

1. Not 100% tested (value guaranteed by design and characterization).

2. Only applicable as a constraint for the Write Status Register command when BPL = 1.

Symbol

Parameter

1.65 V to 3.6 V

2.3 V to 3.6 V

Units

Min

Typ

Max

Min

Typ

Max

fCLK

Maximum Clock Frequency for All Operations

(including 0Bh opcode)

104

MHz

fRDLF

Maximum Clock Frequency for 03h Opcode

(Read Array – Low Frequency)

MHz

fRDDO

Maximum Clock Frequency for 3Bh Opcode

MHz

tCLKH

Clock High Time

tCLKL

Clock Low Time

tCLKR 1

Clock Rise Time, Peak-to-Peak (Slew Rate)

0.1

V/ns

tCLKF 1

Clock Fall Time, Peak-to-Peak (Slew Rate)

0.1

V/ns

tCSH

Chip Select High Time

tCSLS

Chip Select Low Setup Time (relative to Clock)

tCSLH

Chip Select Low Hold Time (relative to Clock)

tCSHS

Chip Select High Setup Time (relative to Clock)

tCSHH

Chip Select High Hold Time (relative to Clock)

tDS

Data In Setup Time

tDH

Data In Hold Time

tDIS 1

Output Disable Time

Output Valid Time

tOH

Output Hold Time

tHLS

HOLD Low Setup Time (relative to Clock)

tHLH

HOLD Low Hold Time (relative to Clock)

tHHS

HOLD High Setup Time (relative to Clock)

tHHH

HOLD High Hold Time (relative to Clock)

tHLQZ 1

HOLD Low to Output High-Z

tHHQX 1

HOLD High to Output Low-Z

tWPS 1,2

Write Protect Setup Time

tWPH 1,2

Write Protect Hold Time

100

tEDPD 1

Chip Select High to Deep Power-Down

µs

tEUDPD.

Chip Select High to Ultra-Deep Power-Down

µs

tSWRST

Software Reset Time

µs

tCSLU

Minimum Chip Select Low to Exit Ultra-Deep Power-Down

tXUDPD

Exit Ultra-Deep Power-Down Time

µs

tRDPD 1

Chip Select High to Standby Mode

µs

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