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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM32H533CE датащи(PDF) 157 Page - STMicroelectronics |
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STM32H533CE датащи(HTML) 157 Page - STMicroelectronics |
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157 / 231 page  DS14539 Rev 1 157/231 STM32H533xx Electrical characteristics 200 Figure 27. Synchronous non-multiplexed NOR/PSRAM read timings Table 79. Synchronous non-multiplexed NOR/PSRAM read timings(1) 1. Evaluated by characterization - Not tested in production. Symbol Parameter Min Max Unit tw(CLK) FMC_CLK period 2Tfmc_ker_ck –0.5 - ns t(CLKL-NExL) FMC_CLK low to FMC_NEx low (x = 0..2) - 1 td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x = 0…2) Tfmc_ker_ck- 0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0.5 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x = 16…25) - 1 td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x = 16…25) Tfmc_ker_ck- 0.5 - td(CLKL-NOEL) FMC_CLK ow to FMC_NOE low - 1 td(CLKH-NOEH) FMC_CLK high to FMC_NOE high Tfmc_ker_ck + 0.5 - tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high 3.5 - th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high 1.5 - t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2.5 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 1.5 - FMC_CLK FMC_NEx FMC_A[25:0] FMC_NOE FMC_D[15:0] D1 D2 FMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tw(CLK) tw(CLK) Data latency = 0 td(CLKL-NExL) td(CLKH-NExH) td(CLKL-AV) td(CLKH-AIV) td(CLKL-NOEL) td(CLKH-NOEH) tsu(DV-CLKH) th(CLKH-DV) tsu(DV-CLKH) th(CLKH-DV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) tsu(NWAITV-CLKH) t h(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) MS32759V1 FMC_NADV td(CLKL-NADVL) td(CLKL-NADVH) |
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