DCR

L

R

C

Vout

SW

CSN

CSP

2.49kW

2.49kW

UCD7232

www.ti.com

SLUSAH3

– MAY 2011

LS GATE

The LS Gate signal directly drives the gate of the low-side power FET. It provides high current drive to quickly

charge the gate capacitance of the FET, which is often considerably larger than the high-side FET. When

commanded on, the LS Gate is driven to the VGG pin potential. The current return path for the driver is provided

by the PGND pin. When commanded off, the LS Gate pin is driven to the PGND potential. The traces from the

LS Gate and the PGND pins to the low-side FET gate and source pins should be short and wide to minimize

parasitic inductance and resistance.

CSP, CSN

These pins are the input to the differential current sense amplifier. The Current Sense Positive (CSP) pin

connects to the non-inverting input, the Current Sense Negative (CSN) connects to the inverting input. This

amplifier provides the means to monitor and measure the output current of the power stage. The circuitry can be

used with a discrete, low value, series current sense resistor, or can make use of the popular inductor DCR

sense method.

The DCR method is illustrated in Figure 3. A series resistor and capacitor network is added across the buck

stage power inductor. It can be shown that when the value of L/DCR is equal to RC, then the voltage developed

across the capacitor, C, is a replica of the voltage waveform the ideal current would induce in the dc resistance

(DCR) of the inductor. This method does not detect changes in current due to changes in inductance value

caused by saturation effects. The value used for C should be in the 0.1

µF to 2.2µF range. This keeps the

impedance of the sense network low, which reduces its susceptibility to noise pickup from the switching node.

The trace lengths of the CSP and CSN signals should be kept short and parallel. To aid in rejection of high

frequency common-mode noise, a series 2.49k resistor should be added to both the CSP and CSN signal paths,

with the resistors being placed close to the pins at the package. This small amount of additional resistance

slightly lowers the current sense gain.

Power inductors are selected for the lowest possible DCR to minimize losses. Typical DCR values range from

0.5m

Ω to 5mΩ. With a load current of 20A, the voltage presented across the CSP and CSN pins is only in the

range of 10mV to 100mV. Keep in mind that this small differential signal is riding on a large common mode signal

that is the dc output voltage. This makes the current sense signal challenging to process.

Figure 3. DCR Current Sense

The UCD7232 uses switched capacitor technology to perform the differential to single-ended conversion of the

sensed current signal. This technique offers excellent common mode rejection. The differential CSP-CSN signal

is amplified by a factor of 97.8 and then a fixed 500mV pedestal voltage is added to the result. This signal is

presented to the IMON pin.

When using inductors with DCR values of 2m

Ω or higher, it may be necessary to attenuate the input signal to

prevent saturation of the current sense amplifier. This is easily accomplished through the addition of resistor R2

as shown in Figure 4.

Copyright

© 2011, Texas Instruments Incorporated

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