UCD7232

SLUSAH3

– MAY 2011

www.ti.com

Assuming VGG = 6.2V and Fsw = 500kHz, a typical Qg for a low-side FET is 50nC. A typical high-side FET Qg is

13nC. This combination creates an IGATE_AVE of 31.5mA. If the switching frequency was doubled, the current

draw would double to 63mA. If VIN = 12V and the internal VGG linear regulator is being used, the power

dissipation in the VGG regulator, for this case, at 500kHz operation, is 183mW. At 1MHz, it increases to 365mW.

Keep in mind that this is not the total power dissipation of the driver, only the portion dissipated in the VGG

regulator. Good thermal layout techniques are required for this device.

VGG DIS

This pin, when asserted high, disables the on-chip VGG linear regulator. When tied low, the VGG linear regulator is

used to derive VGG from VIN. This pin is designed to be permanently tied high or low depending on the power

architecture being implemented. It is not intended to be switched dynamically while the device is in operation.

SW

The SW pin connects to the switching node of the power conversion stage. It acts as the return path for the

high-side gate driver. When configured as a synchronous buck stage, the voltage swing on SW normally

traverses from below ground to well above VIN. A power Schottky diode should be connected from this pin to

PGND to clamp the negative voltage swing on this pin to less than 1V. A series 1

Ω resistor connects this pin to

the actual switching node. It acts as a current limiting resistor when the Schottky diode is clamping negative

voltage swings. The diode should be rated for at least 0.5A of current and exhibit a breakdown voltage of at least

30V. Small-signal Schottky diodes should not be used.

Parasitic inductance in the high-side FET and the output capacitance (Coss) of both power FETs form a resonant

circuit that can produce high frequency (

>100MHz) ringing on this node. The voltage peak of this ringing, if not

controlled, can exceed twice VIN. Care must be taken to not allow the peak ringing amplitude to exceed twice the

value of the input voltage, even if that voltage amplitude is within the Absolute Maximum rating limit for the pin. In

many cases, a series resistor and capacitor snubber network connected from the switching node to PGND can

be helpful in damping the ringing and decreasing the peak amplitude. It is recommended that provisions for

snubber network components be provided during the layout of the printed circuit board. If testing reveals that the

ringing amplitude at the SW pin exceeds twice VIN, then the snubber components need to be populated.

BST

The BST pin provides the drive voltage for the high-side FET. A bootstrap capacitor is connected from this pin to

the SW node. Internally, a diode connects the BST pin to the VGG supply. In normal operation, when the

high-side FET is off and the low-side FET is on, the SW node is pulled to ground and, thus, holds one side of the

bootstrap capacitor at ground potential. The other side of the bootstrap capacitor is clamped by the internal diode

to VGG. The voltage across the bootstrap capacitor at this point is the magnitude of the gate drive voltage

available to switch-on the high-side FET. The bootstrap capacitor should be a low ESR ceramic type, with a

recommended minimum value of 0.22

µF. A minimum voltage rating of 16V or higher is recommended.

HS GATE

The HS Gate signal directly drives the gate of the high-side power FET. It provides high current drive to charge

the gate capacitance of the FET rapidly to insure that it makes the transition from off to on as quickly as possible

to minimize switching losses. When commanded on, the HS Gate is driven to the BST pin potential. As the FET

begins to turn on, the SW will quickly rise to the VIN potential. This voltage swing is coupled by the bootstrap

capacitor to the BST pin. The net result is that the BST pin voltage, and thus the HS Gate voltage, is always

equal to VSW + VGG. As the FET gate charges, the current return path for the driver is provided by the SW pin.

When the HS Gate is commanded off, the driver pulls the pin to the SW potential. As the FET turns off, the SW

pin will swing quickly to slightly below ground. Once again, this voltage swing is coupled to the BST pin by the

bootstrap cap. The HS Gate circuitry is referenced to the SW pin and floats with the SW signal swing. The

circuitry loop from the HS Gate pin to the gate of the FET and from the source of the high-side FET to the SW

pin should kept as small and tight as possible to limit stray inductance. Likewise, the loop from the BST pin to the

bootstrap capacitor and back to the SW pin should be kept small and tight.

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© 2011, Texas Instruments Incorporated