UCD7232

SLUSAH3

– MAY 2011

www.ti.com

CALCULATING THE DCR CURRENT SENSE COMPONENTS

With an inductor selected, the next step is to calculate the value of the DCR current sensing components. While

the inductor has a nominal room temperature resistance of 1.2m

Ω, when in use, the winding temperature will be

elevated. Copper has a positive temperature coefficient of 3800ppm/

°C. If we assume a typical temperature rise

of 20

°, then the winding resistance will increase by 7.6% to approximately 1.3mΩ. This DCR value will be used in

the following calculations.

With 20A of load current through the inductor, the voltage drop due to the DCR will be 1.3

× 20 = 26mV. This will

be amplified by a factor of 48 by the current sense amplifier within the UCD7232. This will boost the signal to

1.25V. The internal circuitry then adds a 0.5V pedestal to the amplified signal which results in 1.75V at the IMON

pin. This voltage is within the 2.0V dynamic range of the current measurement and fault detection circuitry of the

controller, so the design can make use of the current sense network shown in Figure 3. No attenuation of the

signal is necessary. R2 in Figure 7 is not required and does not have to be loaded. (If a higher DCR inductor

were selected, attenuation of the current sense signal might be required, and, in that case, R2 would be

populated.)

The values for the current sense RC network (R1 and C6) around the inductor can now be calculated. The

requirement is L/DCR = RC. Let C = 1

µF. Using 1µH for L and the warm DCR value of 1.3mΩ for DCR, the

calculated value for R is 769

Ω. The nearest standard 1% value is 768Ω. Thus, C6 = 1µF and R1 = 768Ω.

The CSP and CSN pins are sensitive to noise pickup. Signal traces to these pins should be kept short and away

from the switching node and the gate drive traces. They should be shielded by ground planes and adjacent

ground fingers if possible. Series 2.49k

Ω resistors R3 and R4 are added close to the CSP and CSN pins to help

attenuate noise. Further reduction in noise can be achieved by placing the current sense capacitor, C6, close to

R3 and R4.

FET SELECTION

At a minimum, the FETs used in the power stage must have a VDS breakdown rating of at least 1.5 times the

maximum input voltage. This headroom is required since the peak voltage on the switching node is always higher

than the input voltage due to ringing caused by energy storage in the parasitic inductance of the FETs and the

PCB traces. With good layout practices and the use of a snubber network, the peak voltage on the FETs can be

limited to 1.5 times Vin. In this example, a minimum VDS rating of 21V is required to accommodate a 14V input

voltage.

The high-side FET should be selected to handle current pulses equal to twice the steady state current rating of

the power stage. This allows headroom for ripple current, load transients, and brief over-current events. Note that

this is a pulsed current requirement, not a continuous current requirement. The average current in the high-side

FET is roughly equal to the load current times the duty cycle. For this example, an ID peak current rating of 40A

or higher is the target. The average current in the FET will be highest at full load, at the lowest input voltage and

highest output voltage. In this example, VIN(min) is 6V and Vout(max) is 3.3V. At full load, the average FET

current will be 11A. Adding a 20% safety margin to this value produces a 13.2A steady state drain current

requirement.

When converting power from input voltages of approximately 8V and higher, switching losses begin to dominate

over conduction losses in the high-side FET. That means RDS(ON) is not the primary specification that drives

high-side FET selection. Low gate charge (Qg), low gate-to-drain charge (Qgd), and low gate resistance (Rg)

become more important parameters. One of the most useful figures of merit is the product of on-resistance and

gate charge (Qg

× RDS(ON)). The lower the number, the better the FET.

FETs are characterized at several standard gate enhancement voltages. The most popular are VGS voltages are

4.5V and 10V. Since our design is using approximately 6V of gate drive, the datasheet values of RDS(ON) at

4.5VGS will be of greatest interest. Be cautious of FETs that are characterized at 2.5VGS. These are low-threshold

FETs that are useful when converting power at input voltages below 6V. However, due to subtle, but serious,

side effects of the low threshold voltage, they are best avoided when converting power at voltages above 6V.

For this design the TI CSD16322Q5 is an excellent choice for the high-side FET (Q1). It has low charge, an

impressive figure of merit, and low Qgd. It exhibits low switching losses. It is produced in an industry standard,

thermally enhanced, 5

× 6mm package. It has more than enough current handling capability for this 20A design.

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© 2011, Texas Instruments Incorporated