UCD7232

SLUSAH3

– MAY 2011

www.ti.com

DETAILED DESCRIPTION

GENERAL

The UCD7232 is designed primarily to be a synchronous buck driver with current measurement and fault

detection capabilities that make it an ideal partner with digital power controllers. This device incorporates two

high-current gate drive stages and sophisticated current measurement circuitry that allows for the monitoring and

reporting of output load current. Two separate fault detection blocks protect the power stage from excessive load

current or short circuits. On-chip thermal shutdown protects the device in case of severe over-temperature

conditions. Detected faults immediately truncate the power conversion cycle in progress, without controller

intervention, and assert a digital fault flag (FLT). Gate drive voltage is supplied by an on-chip linear regulator. If

desired, this regulator can be disabled and an external gate drive voltage can be supplied. Mode selection pins

allow the device to be used in synchronous mode or independent mode. In synchronous mode, the high-side and

low-side gate timing is controlled by a single PWM input. Anti-cross-conduction dead-time intervals are applied

automatically to the gate drives. In independent mode, the high-side and low-side gate drive signals are

controlled directly by the PWM and SRE pins. The automatic dead-time logic is disabled in this mode. When

operating in synchronous mode, the use of the low-side FET can be disabled under the control of the SRE pin.

This feature facilitates start-up into a pre-bias voltage and is also used in some applications to reduce power

consumption at light loads.

PWM INPUT

The PWM input pin accepts the digital signal from the controller that represents the desired high-side FET

on-time duration. This input is designed to accept 3.3V logic levels, but is also tolerant of 5V input levels. The

SRE Mode pin sets the behavior of the PWM pin. When the SRE Mode pin is asserted high, the device is placed

in synchronous mode. In this mode, the timing duration of the high-side gate drive and the low-side gate drive

are both controlled PWM input signal. When PWM is high, the high-side gate drive (HS Gate) is on and the

low-side gate drive (LS Gate) is off. When PWM is low, the high-side gate drive is off and the low-side gate drive

is on. Automatic anti-cross-conduction logic monitors the gate to source voltage of the FETs to verify that the

proper FET is turned off before the other FET is turned on. When the SRE Mode pin is asserted low, the device

is placed in independent mode. In this mode the PWM input only controls the high-side gate drive. When PWM is

high, the high-side gate drive is on. The low side FET in independent mode is directly controlled by the SRE pin.

No anti-cross-conduction logic is active in independent mode. The user must insure that the PWM and SRE

signals do not overlap.

The PWM input supports a 3-state detection feature. It can detect if the PWM input signal has entered a 3-state

mode. When 3-state mode is detected, both the high-side and low-side gate drive signals are held off. To support

this mode, the PMW input pin has an internal pull-up resistor of approximately 50k

Ω to 3.3V. It also has a 50kΩ

pull-down resistor to ground. During normal operation, the PWM input signal swings below 0.8V and above 2.5V.

If the source driving the PWM pin enters a 3-state or high impedance state, the internal pull-up/pull-down

resistors will tend to pull the voltage on the PWM pin to 1.65V. If the voltage on the PWM pin remains within the

0.8V to 2.5V 3-state detection band for longer than the tHLD_R 3-state detection hold-off time, then the device

enters 3-state mode and turns both gate drives off. This behavior occurs regardless of the state of the SRE Mode

and SRE pins. When exiting 3-state mode, PWM should first be asserted low. This will insure that the bootstrap

capacitor is recharged before attempting to turn on the high-side FET.

The logic threshold of this pin typically exhibits 900mV of hysteresis to provide noise immunity and insure

glitch-free operation of the gate drivers.

SRE INPUT

The SRE (Synchronous Rectifier Enable) pin is a digital input with an internal 10k

Ω pull-up resistor to 3.3V. It is

designed to accept 3.3V logic levels, but is also tolerant of 5V levels. The SRE Mode pin sets the behavior of the

SRE pin. When the SRE Mode pin is asserted high, the device is placed in synchronous mode. In this mode, the

input, when asserted high, enables the operation of the low-side synchronous rectifier FET. The state of the

low-side gate drive signal is governed by the PWM input. When SRE is asserted low while in synchronous mode,

the low-side FET gate drive is continuously held low, keeping the FET off. While held off, current flow in the

low-side FET is restricted to its intrinsic body diode. When the SRE Mode pin is asserted low, the device is

placed in independent mode. In this mode, the state of the low-side gate drive signal follows the state of the SRE

signal. It is completely independent of the state of the PWM signal. No anti-cross-conduction logic is active in

independent mode. The user must insure that the PWM and SRE signals do not overlap.

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Copyright

© 2011, Texas Instruments Incorporated