UCD7232

www.ti.com

SLUSAH3

– MAY 2011

PIN FUNCTIONS

PIN

I/O

FUNCTION

QFN-20

NAME

1

HS Sense

I

High-side current fault threshold set pin. A resistor is connected from this pin directly to the drain of the

high-side FET. The voltage drop across this resistor sets the maximum voltage drop allowed across the

high-side FET after the blanking time set by RDLY. Exceeding this threshold will assert FLT and truncate

the HS Gate pulse. This pin sinks a constant 100

µA of current.

2

FLT

O

Fault Flag. The FLT signal is a 3.3v digital output which is asserted high when an over-current,

over-temperature, or UVLO fault is detected. After an over-current event is detected, the flag is reset low on

the falling edge of the next PWM pin, provided the over-current condition is no longer detected during the

on-time of the PWM signal. For UVLO and over-temperature faults, the flag is reset when the fault condition

is no longer present.

3

SRE Mode

I

Synchronous Rectifier Enable Mode select pin. When high, the high-side and low-side gate drive timing is

controlled by the PWM pin. Anti-cross-conduction logic prevents simultaneous application of high-side and

low-side gate drive. When low, independent operation of the high-side and low-side gate is selected. The

high-side gate is directly controlled by the PWM signal. The low-side gate is directly controlled by the SRE

signal. No anti-cross-conduction circuitry is active in this mode. This pin should not be left floating.

4

SRE

I

Synchronous Rectifier Enable or Low-Side Input. This pin is a digital input capable of accepting 3.3V or 5V

logic level signals. A Schmitt trigger input comparator desensitizes this pin from external noise. When SRE

Mode is high, this signal, when low, disables the synchronous rectifier FET. The LS Gate signal is held off.

When SRE Mode is high, this signal, when high, allows the LS Gate signal to function according to the state

of the PWM pin. When SRE Mode is low, this pin is a direct input to the LS Gate driver.

5

ILIM

I

Output current limit threshold set pin. The voltage on this pin sets the fault threshold voltage on the IMON pin.

The nominal threshold voltage range is 0.5 V to 3.0 V. When V(IMON) exceeds V(ILIM), the FLT pin is

asserted and the HS Gate pulse is truncated.

6

IMON

O

Current Sense Linear Amplifier Output. The output voltage level on this pin represents the average output

current. V(IMON) = 0.5 V + 50.2 (V(CSP) – V(CSN)).

7

CSN

I

Inverting input of the output current sense amplifier and current limit comparator.

8

CSP

I

Non-inverting input of the output current sense amplifier and current limit comparator.

9

BP3

O

Bypass capacitor for internal 3.3V supply. Connect a 1

µF (minimum) ceramic capacitor from this pin to

AGND.

10

PWM

I

PWM input. This pin is a digital input capable of accepting 3.3 V or 5 V logic level signals. A Schmitt trigger

input comparator desensitizes this pin from external noise. When SRE Mode is high, this pin controls both

gate drivers. When SRE Mode is low, this pin only controls the high-side driver. This pin can detect when

the input drive signal has switched to a high impedance (3-state) mode. When the high impedance mode is

detected, both the HS Gate and LS Gate signals are held low.

11

RDLY

I

Requires a resistor to AGND for setting the Current Sense blanking time for the high-side current sense

comparator and output current limit circuitry.

12

AGND

–

Analog ground return for all circuits except the LS Gate driver.

13

VGG DIS

I

VGG Disable pin. When pulled high, the on-chip VGG linear regulator is disabled. When disabled, an

externally supplied gate voltage must be connected to the VGG pin. Connect this pin to AGND to use the

on-chip regulator.

14

PGND

–

Power Ground pin. This pin provides a return path for the low-side gate driver.

15

LS Gate

O

The Low-Side high-current driver output. Drives the gate of the low-side synchronous MOSFET between

VGG and PGND.

16

Vin

I

Input Voltage to the buck power stage and driver circuitry

17

VGG

I/O

Gate Drive voltage supply. When VGG DIS is low, VGG is generated by an on-chip linear regulator. Nominal

output voltage is 6.2 V. When VGG DIS is high, an externally supplied gate voltage can be applied to this

pin. Connect a 4.7

µF capacitor from this pin to PGND.

18

BST

I/O

Floating bootstrap supply for high side driver. Connect the bootstrap capacitor between this pin and the SW

node. The bootstrap capacitor provides the charge to turn on the high-side MOSFET.

19

HS Gate

O

The High-Side high-current driver output. Drives the gate of the high side buck MOSFET between BST and

SW.

20

SW

I/O

Switching node connection to buck inductor. This pin provides a return path for the high-side gate driver.

PP

PAD

–

Power Pad. Connect directly to AGND for better thermal performance and EMI reduction.

Copyright

© 2011, Texas Instruments Incorporated

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