UCD7232

www.ti.com

SLUSAH3

– MAY 2011

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

TYP

MAX

UNIT

VIN

Power Input Voltage (Internally generated VGG)

4.7

12

15

V

VIN

Power Input Voltage (Externally supplied VGG)

2.2

–

15

V

VGG

Externally supplied gate drive voltage

4.6

6

6.5

V

TJ

Operating junction temperature range

–40

–

125

°C

ELECTRICAL CHARACTERISTICS

VIN = 12V, 4.7 µF from VGG to PGND, 1 µF from BP3 to AGND, 0.22 µF from BST to SW, TA = TJ = –40°C to 125°C,

RDLY = 8.06k

Ω, SRE Mode = 3.3V, VGG DIS tied to AGND (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY SECTION

Supply current

Outputs not switching, VIN = 5 V, PWM = LOW

8

10

mA

Supply current

Outputs not switching, VIN = 15 V, PWM = LOW

8

10

mA

GATE DRIVE UNDER-VOLTAGE LOCKOUT

VGG

UVLO OFF

VGG rising

4.4

4.6

V

VGG

UVLO ON

VGG falling

4.1

4.3

V

VGG

UVLO hysteresis

80

mV

VGG SUPPLY GENERATOR

VIN ≥ 7 V, I_VGG ≤ 100 mA

5

V

VGG

VIN = 12 V, I_VGG ≤ 80 mA

5.6

6.2

6.8

V

Dropout

VIN = 4.75 V, I_VGG ≤ 100 mA

350

mV

DIGITAL INPUT SIGNALS (PWM, SRE)

VIH_PWM

Positive-going input threshold voltage

1.8

2

V

VIL_PWM

Negative-going input threshold voltage

0.80

0.90

V

PWM

Input voltage hysteresis, (VIH – VIL)

0.90

V

VIH_SRE

Positive-going input threshold voltage

1.5

1.7

V

VIL_SRE

Negative-going input threshold voltage

0.9

1.00

V

SRE

Input voltage hysteresis, (VIH – VIL)

0.45

V

VPWM = 5 V

140

IPWM

Input current

VPWM = 3.3 V

70

µA

VPWM = 0 V

–63

VSRE = 5 V

190

ISRE

Input current

VSRE = 3.3 V

12

µA

VSRE = 0 V

–330

VPWM transition from 0 V to 1.65 V,

tHLD_R

3-state hold-off time (1)

450

600

750

ns

Time until VLS Gate falls to 0 V

VPWM transition from 1.65 V to 0 V,

tHLD_R

3-state recovery time (1)

150

330

500

ns

Time until VLS Gate rises to VGG

PWM minimum pulse to force HS gate

tmin

CL = 3 nF at HS gate, VPWM = 3.3 V

50

ns

pulse(1)

PWM frequency(1)

QgHS + QgLS < 46 nC, VGG = 6.4 V

2

MHz

OUTPUT CURRENT LIMIT (ILIM)

ILIM Input impedance(1)

250

k

Ω

ILIM set point range(1)

0.5

3

V

FLT output high level

ILOAD = –2 mA

2.7

3.3

V

FLT output low level(1)

ILOAD = 2 mA

0.1

0.6

V

V(ILIM) = 1.50 V, (CSP – CSN) = 20 mV,

Fault detection time. Delay until HS Gate

tFAULT_HS

100

150

ns

falling.(1)

CSN = 1.80 V

V(ILIM) = 1.50 V, (CSP – CSN) = 20 mV,

Fault detection time. Delay until LS Gate

tFAULT_LS

150

200

ns

rising.(1)

CSN = 1.80 V

(1)

As designed and characterized. Not 100% tested in production.

Copyright

© 2011, Texas Instruments Incorporated

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