UCD7232

SLUSAH3

– MAY 2011

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COMPUTING VALUES FOR RDLY and RHS Sense

RDLY sets the amount of blanking time for the high speed comparator that monitors the voltage drop across the

high-side FET during its on-time. This comparator fires when the high-side FET is conducting too much current.

Because of the time it takes for ringing to decay on the switching node, the comparator

“decision” should be

delayed for a short amount of time after the high-side FET is turned on. With a proper snubber network, a delay

time of 100ns should be sufficient to allow for proper over-current detection. Using the formula in the RDLY

section, value of 8.03k

Ω produces a 100ns delay. The nearest standard value is 8.06kΩ, so this is the value

used for R7.

Note that when the duty cycle is of shorter duration than the blanking time, the high-side fault sensing circuit is

blanked for the entire time. Thus there is no high-side FET protection when the duty cycle duration is shorter

than the RDLY blanking time. This condition commonly occurs during soft-start, when the output voltage is being

ramped up from zero, or when operating at high switching frequencies and attempting to produce low output

voltages from high input voltages. Keep this in mind when setting operating frequency and input to output voltage

ratios.

The first step in selecting a value for RHS Sense, is to determine what is the maximum allowable voltage drop

across the high-side FET. This is calculated from the RDS(ON) of the FETs, taking into account its likely junction

temperature when operating at the maximum current point, and by the maximum allowable FET current. The

RDS(ON) value on the data sheet is specified at 25°C and at a particular VGS voltage, typically 4.5V and 10V. In

this case, neither value is correct, since this design will applying approximately 6.2V to the gate. Additionally,

FET RDS(ON) has a high, positive temperature coefficient of typically 4000ppm/°C. This means for a 100°C rise in

junction temperature, the on-resistance will go up by 40%. For a fault condition, using a 125

°C junction

temperature is a reasonable assumption. A valid estimate of the RDS(ON) with 6V of enhancement at 125°C of the

CSD16322Q5 is 5m

Ω.

The second step is to calculate a maximum current value for the high-side FET. Use 150% of the rated output

current value, plus one half of the peak-to-peak inductor ripple current. For this example this gives a value of

1.5

× 20 × ½ × 5 = 32.5A. This level of current provides headroom for transients, start-up surge currents, and the

increase in inductor ripple current as the inductance falls with increasing current. The maximum allowable

voltage drop can now be calculated as just the product of the maximum current value and the

“hot” RDS(ON). This

produces a value of 162.5mV for this design. This should not be regarded as a precision value. Keep in mind

that the high-side FET protection is meant to be the last protection for the power stage to prevent catastrophic

damage to the power train. The maximum voltage drop value should be set high enough to prevent nuisance

trips of the protection circuitry under normal operation.

The value for RHS Sense can now be calculated. Its resistance, in kΩ, is equal to the maximum high-side voltage

drop, in mV, divided by 100. In our example this produces a value of 1.63k

Ω. Rounding this up to the nearest

standard value of 1.65k

Ω gives the value for R12.

SETTING THE ILIM THRESHOLD

The primary fault protection mechanism in the UCD7232 is the output current detection circuitry. An internal

comparator monitors the voltage on the ILIM and IMON pins. When the voltage on IMON exceeds the voltage on

ILIM, the FLT pin is asserted and power conversion stops. If a UCD92xx controller is used to drive the power

stage, it can also monitor the voltage on IMON and detect an over current condition. The threshold for the fault trip

point is easily set by firmware, making it flexible. The maximum current sense input voltage that can be correctly

digitally sampled by a UCD92xx controller is 2.5V. (The maximum programmable limit for the fast OC threshold is

2V.) For this design it was decided to use this 2.5V level as the threshold for the ILIM comparator. In this way the

digitally programmable controller will detect a slowly changing OC fault, and the ILIM comparator in the driver will

protect the system from a sudden increase in current. This corresponds to an output current of approximately

31A. All that needs to be done is to set up a voltage divider that will produce 2.5V at the ILIM pin. The BP3 pin

provides a convenient source of clean, regulated 3.3V. The value of R5 was arbitrarily set to 10k

Ω. Simple math

produces a value of 31.6k

Ω for R6. These values produce the desired 2.5V on ILIM. The voltage divider only

draws 80

μA from the BP3 pin, which is within the allowable limits.

20

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© 2011, Texas Instruments Incorporated