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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SPSB081 датащи(PDF) 25 Page - STMicroelectronics |
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SPSB081 датащи(HTML) 25 Page - STMicroelectronics |
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25 / 137 page  Failure source Failure condition Diagnosis Exit from fail-safe mode SGND Loss of ground at SGND pin FS (global status byte) = 1 SGNDLOSS (SR 6) = 1 Wake-up Read and clear SR1 3.8 Reset output (NRESET) At power-up, the reset signal is low. When VS > VPOR, the RSTB bit is set and SPI registers are set to default values. If V1 is turned on and the voltage exceeds the V1 reset programmable threshold VRTX by SPI, the reset output “NRESET” is pulled up by internal pull-up resistor to V1 voltage after a reset delay time (tRD). This is necessary for a defined start of the microcontroller when the application is switched on. As soon as the NRESET is released, the watchdog timing starts with a long open window. At power down, the device is reset, and control registers are set to default values and RSTB bit is set to “1” (see the following figure). Figure 14. NRESET pin Data in 110 kΩ Data out A reset pulse is generated in case of: • V1 drops below VRTX (configurable by SPI) for t > tUV1 • Watchdog failure • Turn-on of the V1 regulator (VSREG power-on or wake-up from VBAT_standby mode) 3.9 DIAGN output Figure 15. DIAGN pin Data in RDIAGN Data out SPSB081 Reset output (NRESET) DS14048 - Rev 3 page 25/137 |
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