SPSB081 datasheet(45/137 Pages) STMICROELECTRONICS

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4.2.2.2

Operating code

The operating code is used to distinguish between different access modes to the registers of the slave device.

Table 13. Operation codes

OC1

OC0

Description

Write operation

Read operation

Read and clear operation

Read device information

A write operation leads to a modification of the addressed data by the payload if a write access is allowed (for

example, control register, valid data). Beside this a shift out of the content (data present at communication start)

of the registers is performed.

A read operation shifts out the data present in the addressed register at communication start. The payload data

is ignored and internal data are not modified. In addition, a burst read can be performed.

A read and clear operation leads to a clear of addressed status bits. The bits to be cleared are defined first by

address, second by payload bits set to ‘1’. Beside this a shift out of the content (data present at communication

start) of the registers is performed.

Note:

Status registers, which change status during communication could be cleared by the actual read and clear

operation and are not reported in the actual communication or in the following communications. To avoid a loss

of any reported status, it is recommended clear status registers, which are already reported in the previous

communication (selective bitwise clear).

4.2.2.3

Advanced operation codes

To provide beside the separate write of all control registers and the bitwise clear of all status registers, two

advanced operation codes can be used to set all control registers to the default value and to clear all status

registers.

A ‘set all control registers to default’ command is performed when an OpCode ‘11’ at address b’111111 is

performed.

Note:

Please consider that potential device specific write protected registers cannot be cleared with this command as

therefore a device power-on-reset is needed.

A ‘clear all status registers’ command is performed when an OpCode ‘10’ at address b’111111 is performed.

4.2.2.4

Data-in payload

The payload (data byte 1 to data byte 3) is the data transferred to the device with every SPI communication. The

payload always follows the OpCode and the address bits.

For write access the payload represents the new data written to the addressed register. For read and clear

operations the payload defines which bits of the addressed status register is cleared. In case of a ‘1’ at the

corresponding bit position the bit will be cleared.

For a read operation, the payload is not used. For functional safety reasons it is recommended to set unused

payload to ‘0’.

4.2.2.5

SDO frame

The data-out frame consists of 32 bits (GSB + data byte 1 to 3).

The first eight transmitted bits contain the device related status information and are latched into the shift register

at the time of the communication start. These 8 bits are transmitted at every SPI transaction.

The subsequent bytes contain the payload data and are latched into the shift register with the eighth positive SCK

edge.

This could lead to an inconsistency of data between the GSB and payload due to different shift register load

times. Anyhow, no unwanted status register clear should appear, as status information should just be cleared with

a dedicated bit clear after.

SPSB081

Signal description

DS14048 - Rev 3

page 45/137

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