SPSB081 datasheet(78/137 Pages) STMICROELECTRONICS

78 / 137 page

Symbol

Parameter

Condition

Min Typ Max Unit

Item

ten DO tri H(1) DO enable time from tristate to high level

CL = 50 pF, Iload = -1 mA

Pull-down load to GND

100

B.030

td DO(1)

DO delay time

VDO < 0.3 V1 or VDO > 0.7 V1,

CL = 50 pF

B.031

1. Guaranteed by design.

Table 60. CSN timing

Symbol

Parameter

Condition

Min Typ Max Unit Item

tCSN_HI,min(1) Minimum CSN HI time, active mode

Transfer of SPI-command to input

0.5

μs

B.032

tCSNfail(1)

CSN low timeout

ms B.033

1. Guaranteed by design.

Figure 35. SPI transfer timing diagram

CSN high to low: DO enabled

time

DI: data will be accepted on the rising edge of CLK signal

CSN

CLK

Input

Data

DO: data will change on the falling edge of CLK signal

fault bit

new data

old data

CSN low to high: actual data is

transferred to output power switches

time

28 27 26 25

CSN high to low: DO enabled

DI: data will be accepted on the rising edge of CLK signal

time

The SPI can be driven by a microcontroller with its SPI peripheral running in the following mode:

CPOL = 0 and CPHA = 0.

For this mode input data is sampled by the low to high transition of the clock CLK, and output data is changed

from the high to low transition of CLK.

SPSB081

SPI

DS14048 - Rev 3

page 78/137

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