SPSB081 datasheet(115/137 Pages) STMICROELECTRONICS

115 / 137 page

Table 112. Configuration register signals description

Bit

Name

Description

CAN_LOOP_EN

CAN Looping of TxD_C to RxD_C

0 = CAN looping disabled (default)

1 = CAN looping enabled

LIN_TXD_TOUT_EN

LIN TxD timeout detection

0 = LIN TxD timeout detection disabled

1 = LIN TxD timeout detection enabled (default)

LIN_WU_config

Configuration of LIN wake-up behaviour

0 = Wake-up at recessive - dominant - recessive with t_dom > 28 μs (default), (according to LIN ISO

17987-4/2016 and Hardware Requirements for Transceivers version 1.3)

1 = Wake-up at recessive - dominant or dominant - recessive transition

CANTO_NINT_MASK

0 = CAN communication timeout is not masked (default)

1 = CAN communication timeout is masked

WU_NINT_MASK

0 = Wake-up is not masked (default)

1 = Wake-up is masked

DIAGN_EXT

Fail safe output configuration by DIAGN pin

0 = Only fail safe mode is considered (for example watchdog failure; V1 failure; thermal shutdown TSD2),

(default).

1 = DIAGN pin reflects one or more errors such as reported in the GLOBAL STATUS BYTE register by global

status bit not (GSBN)

ICMP_CONFIG_EN

0 writing ICMP = 1 is blocked (writing ICMP=0 is possible); (default)

1 writing ICMP = 1 is possible with next SPI command

bit is automatically reset to 0 after next SPI command

WD_CONFIG_EN

0 = Writing to WD configuration (CR2 [0:1] is blocked (default)

1 = Writing to WD configuration bits is possible with next SPI command bit is automatically reset to 0 after next

SPI command

RES

Reserved

RES

Reserved

MASK_TW

0 = Thermal warning is not masked (default)

1 = Thermal warning is masked

For example it is reported as a global warning (GSB bit 1) but not as a global error (GSB bit 7)

MASK_RSTB

0 = V1_UV reset condition is not masked (default)

1 = V1_UV reset condition is masked

For example reported as a reset (GSB bit 6) but not as a global error (GSB bit 7)

MASK_OL

0 = Open load condition at all outputs are not masked (default)

1 = Open load condition at all outputs are masked

For example. it is reported as a functional error (GSB bit 27) but not as a global error (GSB bit 31)

RES

Reserved

MASK_PLE

0 = Physical layer errors are not masked (default)

1 = Physical layer errors are masked

For example reported as a physical layer error (GSB bit 4) but not as a global error (GSB bit 7)

MASK_GW

0 = Global warning conditions are not masked (default)

1 = Global warning conditions are masked

For example reported as a global warning (GSB bit 1) but not as a global error (GSB bit 7)

SPSB081

Control registers

DS14048 - Rev 3

page 115/137

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