ADF4382ABCCZ datasheet(21/82 Pages) AD

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Data Sheet

ADF4382A

THEORY OF OPERATION

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Rev. A | 21 of 82

It is recommended to increase the fCHSP by multiplying by

five for each repetition of the previous step to reduce to

MOD2WORD ≤ MOD2WORDMAX.

e. Calculate final MOD2WORD.

In order to maximize frequency resolution, the final value of

MOD2WORD is calculated by obtaining the highest integer

multiple of the initial MOD2WORD, that is less than or equal

to the MOD2WORDMAX as follows.

MOD

2WORD =INT

MOD

2WORDMAX

2WORDINITIAL

×MOD

2WORDINITIAL

(19)

MOD

2WORD =INT16777215

1953125

×1953125

(20)

MOD

2WORD =8×1953125

= 15625000

(21)

5. Calculate FRAC2WORD

FRAC

2WORD = INTNREMAINDER

×MOD

2WORD

(22)

FRAC

2WORD = INT0.096

×15625000

(23)

FRAC

2WORD = 1500000

(24)

6. Calculate total N-value using the original formula

N=NINT+FRAC1WORD+FRAC2WORD

MOD

2WORD

MOD

1WORD

(25)

N=80+17716740+1500000

15625000

33554432

= 80.528 (26)

7. Calculate fRFOUT frequency

fVCO=fREF×D×N×OR

(27)

Since fREF = fPFD and fVCO= fRFOUT, hence

fRFOUT=fREF×N

(28)

fRFOUT=250 MHz×80.528 = 20

.132 GHz

(29)

CIRCUIT DESCRIPTION

Reference Input Buffer

The reference frequency of the PLL is applied differentially on

the REFP and REFN pins. These high impedance inputs are self

biased and must be AC-coupled with 1 µF capacitors (see Figure

43 for a simplified schematic). Alternatively, the inputs can be used

single ended by applying the reference frequency at REFP and

bypassing REFN to GND with a 1 µF capacitor.

Figure 43. Reference Input Stage

A high quality signal must be applied to the REFP and REFN inputs

as these inputs provide the frequency reference to the entire PLL.

To achieve the in-band phase noise performance of the ADF4382A,

apply a continuous wave signal or a square wave with a slew rate

of at least 1000 V/µs. See the Reference Source Considerations

section for more information on reference input signal requirements

and interfacing.

The REF_SEL bit (Register 0x030, Bit 5) can be set to either a

CML reference input or sine wave or slow slew-rate reference input.

When REF_SEL is set to 0, the delay matched amplifier (DMA)

buffer is selected. The DMA is optimized for high slew rate signals,

such as square waves or higher frequency and higher amplitude

sine waves. The DMA has a controlled propagation delay from the

reference input to clock output, which eases time zero and over

temperature multichip clock alignment.

When the REF_SEL bit is set to 1, the LNA is selected. The LNA

is optimized for low slew rate signals, such as lower frequency or

lower amplitude sine waves.

The REF_SEL bit must be set correctly to optimize the in-band

phase noise performance and propagation delay, tPD. See Table 7

for recommended settings.

Table 7. REF_SEL Programming

REF_SEL

Sine Wave Slew Rate (V/µs) Square Wave

Optimized tPD

≥1000

Preferred

Yes

<1000

Not applicable

To calculate the slew rate of a sine wave, use the following equa-

tion:

Slew

Rate = 2 × π × f × V

(30)

where:

f is the sine wave frequency.

V is the sine wave amplitude (in V peak)

The FILT_REF bit (Register 0x02F, Bit 6) controls the reference

input LPF of the LNA and must be set only for sine wave signals

less than 20 MHz to limit the wideband noise of the reference. The

FILT_REF bit must be set correctly to reach the normalized in-band

phase noise floor (LNORM). Square wave inputs have FILT_REF set

to 0. Table 8 shows the recommended settings.

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