ADF4382ABCCZ datasheet(29/82 Pages) AD

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Data Sheet

ADF4382A

THEORY OF OPERATION

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Rev. A | 29 of 82

TotalAutocalibration

Time=CAL_VTUNE_TO Time+

fDIV_RCLK + 10×VCO Band Decision Time

+VCAL

Time

(39)

where:

VCO

Band Decision Time=CAL_VCO_TO Time

CAL_COUNT_TO Time+ 5fDIV_RCLK

(40)

fDIV_RCLK= fPFD

2DCLK_DIV1 + DCLK_MODE

(41)

VCAL

Time= 2fDIV_RCLK

(42)

Calibration Time Performance Consideration

When programming the VCO calibration time as per the VCO

Calibration section, the jitter performance can be affected by the

overall calibration time. For applications where taking a longer

time for calibration is not an issue, for example, fixed frequency

applications, it is recommended to program an autocalibration time

of 250 μs to optimize jitter and phase noise performance. For oth-

er applications requiring faster autocalibration times and reduced

overall lock times, an autocalibration time of 100 μs can be used.

However, this time may degrade jitter with temperature changes

over the complete −40°C to +105°C operating range.

Table 21. Recommended Calibration Times

Autocalibration

Time (µs)

CAL_VTUNE_TO

Time

CAL_COUNT_TO

Time (µs)

CAL_VCO_TO

Time (µs)

100

Determined by the

largest loop filter

capacitor

8.5

250

Determined by the

largest loop filter

capacitor

23.5

The CAL_VTUNE_TO time is determined by the charging time of

the maximum value capacitor in the loop filter. Calculate the charge

time by using the following equation:

CAL

_VTUNE_TO Time = C×VI

(43)

where:

C is the largest capacitor value in loop filter.

V is the VTUNE voltage change for lock and leave over tempera-

ture, which is typically 0.8 V.

I is the VCO calibration generator current of 4.2 mA.

CAL_VTUNE_TO Time Calculation

The CAL_VTUNE_TO time is determined by the charging time of

the maximum value capacitor in the loop filter. Calculate the charge

time by using the following equation:

CAL

_VTUNE_TO Time = C×VI

(44)

where:

C is the largest capacitor value in loop filter.

V is the VTUNE voltage change for lock and leave over tempera-

ture, which is typically 0.8 V.

I is the VCO calibration generator current of 4.2 mA.

Core Bias Table

As part of the initialization process, the core bias table must be

programmed with the predefined values provided in the Register

Map section (see Register 0x100 through Register 0x111). These

are specifically optimized VCO bias values for different frequency

bands of operation. After performing a device initialization, the VCO

bias registers are not reprogrammed until a subsequent power-on

reset executes.

RF Output Divider (O)

A 3-bit divider, RFOUT_DIV (Register 11, Bits[7:5]), is used to

divide the frequency seen at the output buffer and feedback divider.

The divide ratio can be set to 1, 2, or 4. See Table 22 for details on

divider settings. RFOUT_DIV is located inside the PLL. Therefore,

any change to RFOUT_DIV requires a change to the N_INT bit

fields (Register 0x010, Bits[7:0] and Register 0x011, Bits[3:0]) to

maintain the same fPFD and results in the PLL losing lock for a few

loop time constants.

Table 22. RFOUT_DIV Programming

RFOUT_DIV

Divisor

Output Frequency Range (GHz)

11.5 ≤ RFOUT ≤ 21

5.75 ≤ RFOUT ≤ 10.5

2.875 ≤ RFOUT ≤ 5.25

Output Invert (INV_RFOUT)

The output invert, INV_RFOUT (Register 0x011, Bit 4), is used to

shift the output signal 180°. INV_RFOUT is located inside the PLL,

and any change to INV_RFOUT results in the PLL losing lock for

few loop time constants.

Feedback Divider (N)

The feedback divider provides a division ratio in the PLL feedback

path. The division ratio consists of the N_INT (Register 0x011,

Bits[3:0] and Register 0x010, Bits[7:0]), FRAC1WORD (Register

0x15, Bit 0; Register 0x14, Bits[23:16]; Register 0x013, Bits[15:8],

and Register 0x012, Bits[7:0]), FRAC2WORD (Register 0x19,

Bits[23:16]; Register0x18, Bits[15:8]; and Register0x17, Bits[7:0]),

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