ADF4382ABCCZ datasheet(12/82 Pages) AD

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Data Sheet

ADF4382A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. A | 12 of 82

Table 6. Pin Function Descriptions (Continued)

Pin No.

Mnemonic

Description

Chip Enable. 3.3 V CMOS input. Does not support 1.8 V CMOS levels. This CMOS input enables the device when

driven high. A logic low disables the device, putting the device in a full power-down state causing the register to

reset. Conversely, the PD_ALL bit powers down the device, but does not reset the registers.

CSB

Serial Port Chip Select. This CMOS input initiates a serial port communication burst when driven low, ending the

burst when driven back high.

SDIO

Serial Data Input/Output. CMOS input and output. When configured as an input, the serial port uses this CMOS

input for data. In 3-wire readback mode (default mode), the SDIO pin outputs data from the serial port during a

read communication burst.

SCLK

Serial Port Clock. This CMOS input clocks serial port input data on its rising edge.

SDO

Optional Serial Data Output. In 3-wire mode (default mode), this three-state CMOS pin remains in a high

impedance state. In 4-wire readback mode, the SDO pin presents data from the serial port during a read

communication burst. When the CSB is de-asserted, SDO returns to a high impedance. Optionally, attach a

resistor of >200 kΩ to prevent a floating output.

V3_LDO

3.15 V to 3.45 V Positive Power Supply Pin for the Internal Low Dropout (LDO) Regulator Circuitry. Short the

V3_LDO pin to the other pins in the 3.3 V Power Supply Group 1.

MUXOUT

Internal Device Multiplexor Output. This output pin can be connected to multiple internal nodes for factory test and

debug purposes.

38, 39

SYNCP, SYNCN

Synchronization Input Signals. Both RF output signals are synchronized to an input signal at these pins. SYNCP

and SYNCN are used for multichip phase synchronization. This differential input can accept both high and low

common-mode input signals (based on the SPI bit setting).

V3_SYNC

3.15 V to 3.45 V Positive Power Supply. Short the V3_SYNC pin to the other pins in the 3.3 V Power Supply Group

42, 43

REFP, REFN

Reference Input Signals. These differential inputs are buffered with a low noise amplifier (LNA) ideally suited for

high slew rates (default mode). For low slew rate reference input signals, an alternate LNA can be selected via

the serial port. Reference inputs are self biased and must be AC-coupled with 1 μF capacitors. Reference inputs

accept differential or single-ended inputs. See the Reference Input Network section for more details.

V3_REF

3.15 V to 3.45 V Positive Power Supply Pin for the PLL Reference Circuitry. Short the V3_REF pin to the other

pins in the 3.3 V Power Supply Group 1.

V3_PFD

3.15 V to 3.45 V Positive Power Supply Pin for PFD Circuitry. Short the V3_PFD pin to the other pins in the 3.3 V

Power Supply Group 1.

V5_CP

4.75 V to 5.25 V Positive Power Supply Pin for Charge Pump Circuitry. Isolate the V5_CP pin from the V5_VCO

supply plane.

Charge Pump Output. This bidirectional current output is normally connected to the external loop filter.

Exposed Pad

GND

Negative Power Supply (Ground). The package exposed pad must be soldered directly to the PCB land. The PCB

land pattern must have multiple thermal vias to the ground plane for both low ground inductance and low thermal

resistance.

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