ADF4382ABCCZ datasheet(52/82 Pages) AD

52 / 82 page

Data Sheet

ADF4382A

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Rev. A | 52 of 82

Table 57. Bit Descriptions for REG0024 (Continued)

Bits

Bit Name

Description

Reset

Access

DCLK_DIV_SEL

Selects Which Bit Field Controls DIV_NCLK Divider 1.

0x0

R/W

0: Div_Nclk_divider1 Controlled by DCLK_DIV1 (Normal Operation).

1: Div_Nclk_divider1 Controlled by DNCLK_DIV1.

[3:2]

DNCLK_DIV1

Controls DIV_NCLK Divider 1 when DCLK_DIV_SEL = 1.

0x0

R/W

00: divide by 1.

01: divide by 2.

10: divide by 4.

11: divide by 8.

[1:0]

DCLK_DIV1

Controls DIV_RCLK Div1. If DCLK_DIV_SEL = 0, then it also controls DIV_NCLK Divider1. See the VCO

Calibration section.

0x0

R/W

00: divide by 1.

01: divide by 2.

10: divide by 4.

11: divide by 8.

Address: 0x025, Reset: 0x00, Name: REG0025

Table 58. Bit Descriptions for REG0025

Bits

Bit Name

Description

Reset

Access

[7:0]

RESYNC_WAIT[7:0]

Sets the waiting time after the calibration and sync pulse to apply the resynchronization. See the Phase

Resynchronization section.

0x0

R/W

Address: 0x026, Reset: 0x00, Name: REG0026

Table 59. Bit Descriptions for REG0026

Bits

Bit Name

Description

Reset

Access

[7:0]

RESYNC_WAIT[15:8]

Sets the waiting time after the calibration and sync pulse to apply the resynchronization. See the

Phase Resynchronization section.

0x0

R/W

Address: 0x027, Reset: 0x00, Name: REG0027

Table 60. Bit Descriptions for REG0027

Bits

Bit Name

Description

Reset

Access

[7:4]

REG027_RSV1

Reserved. ADF4382A register map provides reserved register settings.

0x0

R/W

[3:0]

REG027_RSV0

Reserved. ADF4382A register map provides reserved register settings.

0x0

R/W

Address: 0x028, Reset: 0x00, Name: REG0028

Table 61. Bit Descriptions for REG0028

Bits

Bit Name

Description

Reset

Access

PHASE_RESYNC_RB_SEL

Phase Resync Reset Selector.

0x0

R/W

LSB_P1

Add +1 to Σ-Δ LSB Enable/Disable.

0x0

R/W

VAR_MOD_EN

Enables Auxiliary ΣΔ modulator.

0x0

R/W

[4:2]

DITHER1_SCALE

Selects the LSB Position for Dither 1.

0x0

R/W

EN_DITHER2

Dither Applied to Second Accumulator.

0x0

R/W

EN_DITHER1

Dither Applied to First Accumulator.

0x0

R/W

Address: 0x029, Reset: 0x00, Name: REG0029

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