ADF4382ABCCZ datasheet(51/82 Pages) AD

51 / 82 page

Data Sheet

ADF4382A

analog.com

Rev. A | 51 of 82

Table 52. Bit Descriptions for REG001F (Continued)

Bits

Bit Name

Description

Reset

Access

1010: 4.77 mA.

1011: 5.57 mA.

1100: 6.33 mA.

1101: 7.91 mA.

1110: 9.51 mA.

1111: 11.1 mA.

Address: 0x020, Reset: 0x01, Name: REG0020

Table 53. Bit Descriptions for REG0020

Bits

Bit Name

Description

Reset

Access

EN_AUTOCAL

Enable VCO Calibration.

0x0

R/W

0: VCO calibration disabled.

1: VCO calibration enabled.

EN_RDBLR

Enable Reference Doubler.

0x0

R/W

0: doubler disabled.

1: doubler enabled.

[5:0]

R_DIV

6-Bit Reference Frequency Divider.

0x1

R/W

Address: 0x021, Reset: 0x00, Name: REG0021

Table 54. Bit Descriptions for REG0021

Bits

Bit Name

Description

Reset

Access

[7:0]

PHASE_WORD[7:0]

24 Bits Phase Word.

0x0

R/W

Address: 0x022, Reset: 0x00, Name: REG0022

Table 55. Bit Descriptions for REG0022

Bits

Bit Name

Description

Reset

Access

[7:0]

PHASE_WORD[15:8]

24 Bits Phase Word.

0x0

R/W

Address: 0x023, Reset: 0x00, Name: REG0023

Table 56. Bit Descriptions for REG0023

Bits

Bit Name

Description

Reset

Access

[7:0]

PHASE_WORD[23:16]

24 Bits Phase Word.

0x0

R/W

Address: 0x024, Reset: 0x00, Name: REG0024

Table 57. Bit Descriptions for REG0024

Bits

Bit Name

Description

Reset

Access

REF_CK_FALL

Timing from rising or falling edge of PFD RCLK. Phase Synchronization Settings table.

0x0

R/W

0: DRCLK is timed off of the rising edge of the PFD RCLK.

1: DRCLK is timed off of the falling edge of the PFD RCLK.

[6:5]

REF_DC_SEL

Sets the polarity of the RDIV output before the re-time. See Phase Synchronization Settings table.

0x0

R/W

00: never invert (standard mode).

01: always invert.

10: automatically keep high duty cycle between 50% and 67%.

11: automatically keep high duty cycle between 33% and 50%.

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