ADF4382ABCCZ datasheet(26/82 Pages) AD

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Data Sheet

ADF4382A

THEORY OF OPERATION

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Rev. A | 26 of 82

window time (tLDWIN) for a valid lock condition with the LDWIN_PW

bit field (Register 0x02, Bits[7:5]).

Table 17. LDWIN_PW Programming

LDWIN_PW [7:5] Mode of Operation

000

Integer mode, 500 MHz maximum PFD with bleed ≤ 85 ps

001

Integer mode, 500 MHz maximum PFD with bleed > 85 ps

010

Fractional mode, 250 MHz maximum PFD, RFOUT ≥ 6.4 GHz

011

Fractional mode, 250 MHz maximum PFD, RFOUT ≥ 5 GHz

100

Fractional PLL, 200 MHz maximum PFD, RFOUT ≥ 4 GHz

101

Fractional PLL, 100 MHz maximum PFD, RFOUT ≥ 2 GHz

110

Fractional PLL, 50 MHz maximum PFD, RFOUT ≥ 1 GHz

111

Fractional PLL, 40 MHz maximum PFD, RFOUT ≥ 800 MHz

MUXOUT

The state of the MUXOUT pin is determined by the MUXOUT bits

(Register 0x02E, Bits[7:4]), which allow the user access to various

internal nodes. The MUXOUT pin and MUXOUT bits are commonly

used as an additional lock status output or to debug PLL-related

issues during the hardware and software development phase of a

project. The CMOS_OV bit (Register 0x03D, Bit 5) determines if

the logic high level for the MUXOUT pin, LKDET pin, SDO pin, and

SDIO pin is 3.3 V or 1.8 V.

Figure 49. MUXOUT

Temperature Sensor

The temperature sensor is composed of an 8-bit ADC, which

measures the proportional to absolute temperature (PTAT) voltage

with respect to the reference voltage (VREF) of a bandgap. The

purpose of the temperature sensor is to measure changes in the

die temperature and not the absolute junction temperature. The

maximum ADC clock frequency is 400 kHz. The ADC clock is

generated from the RCLK.

Figure 50. Temperature Sensor

Before an ADC measurement can occur, program the registers of

the ADF4382A as shown in Table 18.

Table 18. ADC Register Setup

Bit Fields

Value

EN_DRCLK, EN_DNCLK,

EN_ADC_CNV

ADC_ST_CNV, EN_ADC,

EN_ADC_CLK

PD_ADC

After the bits in Table 18 are programmed, start an ADC conversion

with a register write to Register 0x054 setting ADC_ST_CNV =

1. An ADC conversion requires 17 clock cycles to complete. In

status. During a conversion, ADC_BUSY is set to 1, and when the

conversion is complete, ADC_BUSY is set to 0. Measurements are

recorded in the CHIP_TEMP bit field, Bits[8:0], in Register 0x05B

and Register 0x05C. The value read back represents the junction

temperature in degrees celsius. The MSB (Bit 8) indicates positive

or negative temperature i.e. when Bit 8 = 1, the temperature read

back is negative.

Double Buffering

Double buffering refers to a main and subordinate configuration for

the bit fields shown in Table 19.

Only the subordinate bit fields control the actual state of the

ADF4382A. When double buffering is enabled for a bit field, the

serial interface only writes to the main bit field. The subordinate

bit field retains its previous value until a register write is sent to

fields are automatically loaded to their respective subordinate bit

fields. Writing to Register 0x010 also starts the autocalibration of

the VCO (see the Standard Power-Up and Initialization Sequence,

Automatic VCO Calibration section), which allows the user to up-

date several bit fields that change the output frequency of the

ADF4382A and starts a new VCO calibration on the same register

write. When double buffering is disabled, the SPI writes directly to

the subordinate bit field.

Table 19. Double Buffer Enabled Bit Fields

Double Buffer Enabled Bits

Double Buffered Bit Fields

Not applicable, always enabled

N_INT, R_DIV, EN_RDBLR, CP_I

RFOUTODIV_DB

RFOUT_DIV

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