ADF4382ABCCZ datasheet(4/82 Pages) AD

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Data Sheet

ADF4382A

SPECIFICATIONS

analog.com

Rev. A | 4 of 82

3.3 V Supply Group 1 pins voltage (V3.3V_1) = 3.3 V Supply Group 2 pins voltage (V3.3V_2) = 3.15 V to 3.45 V, V5_VCO voltage (V5V_VCO) =

5V_CP voltage (V5V_CP) = 5V_CAL voltage (V5V_CAL) = 4.75 V to 5.25 V, all voltages are with respect to GND, and TA = −40°C to +105°C,

operating temperature range, unless otherwise noted.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

REFERENCE INPUTS (REFP and REFN)

Input Frequency

fREF

4500

MHz

Input Signal Level

VREF

0.5

2.6

V p-p

Refer to Figure 43

Minimum Input Slew Rate

100

V/μs

Input Duty Cycle

Self Bias Voltage

1.85

Input Resistance

kΩ

Differential

Input Capacitance

Differential

Input Current

µA

REFERENCE PEAK DETECTOR

Input Frequency

4500

MHz

Minimum Input Signal Detected (REF_OK = 1)

200

mV p-p

fREF = 100 MHz, single-ended sine wave

Maximum Input Signal Not Detected (REF_OK = 0)

160

mV p-p

fREF = 100 MHz, single-ended sine wave

REFERENCE DIVIDER

All integers included

REFERENCE DOUBLER

Input Frequency

2000

MHz

EN_RDBLR = 1

PHASE/FREQUENCY DETECTOR (PFD)

Input Frequency

fPFD

Integer Mode

5.4

625

MHz

Integer mode, for all values of the N divider,

excluding 15 and 28 to 31

5.4

540

MHz

For the N divider values 15 and 28 to 31

Fractional Mode

5.4

250

MHz

EFM3_MODE = 0 and EFM3_MODE = 4

5.4

220

MHz

EFM3_MODE = 5

SYNCHRONIZATION INPUTS (SYNCP and SYNCN)

Input Signal Level

VREF

0.4

2.6

V p-p

Low voltage differential signaling (LVDS)

mode, differential

0.5

2.6

V p-p

Current mode logic (CML) mode, differential

Self Bias Voltage

1.3

LVDS mode

1.85

CML mode

Synchronization to Reference Setup Time

400

Common-mode voltage (VCM) set to self bias

voltage, VCM = 0.8 V p-p

Synchronization to Reference Hold Time

600

VCM set to self bias voltage, VCM = 0.8 V p-p

Input Resistance

kΩ

Differential

Input Capacitance

Differential

Input Current

μA

CHARGE PUMP (CP)

Output Current

ICP

Minimum

0.79

Set by the CP_I bit fields

Maximum

11.1

Set by the CP_I bit fields

Output Current Source and Sink

Accuracy

±2

All setting, CP voltage (VCP) = VCP/2

Matching

±2

All setting, VCP = VCP/2

Output Current vs. Output Voltage Sensitivity

0.2

% V/V

VCP1

Output Current vs. Temperature

280

ppm/C

VCP = VCP/2

Output High-Z Leakage Current

−0.01

μA

Minimum ICP, VCP1

−0.3

μA

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