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ADF4382ABCCZ датащи(PDF) 2 Page - Analog Devices

номер детали ADF4382ABCCZ
подробное описание детали  Microwave Wideband Synthesizer with Integrated VCO
PDF  82 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

ADF4382ABCCZ датащи(HTML) 2 Page - Analog Devices

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Data Sheet
ADF4382A
TABLE OF CONTENTS
analog.com
Rev. A | 2 of 82
Features................................................................ 1
Applications........................................................... 1
General Description...............................................1
Functional Block Diagram......................................1
Specifications........................................................ 4
Serial Interface Timing Characteristics...............8
Phase Adjust 2-Wire Interface............................9
Absolute Maximum Ratings.................................10
Thermal Resistance......................................... 10
Transistor Count...............................................10
Electrostatic Discharge (ESD) Ratings.............10
ESD Caution.....................................................10
Pin Configuration and Function Descriptions.......11
Typical Performance Characteristics................... 13
Theory of Operation.............................................19
Introduction.......................................................19
Output Frequency.............................................20
Circuit Description............................................ 21
Applications Information...................................... 32
Power-Up and Initialization Sequence............. 32
Loop Filter Design............................................ 34
Loop Filter Layout Considerations....................34
Reference Source Considerations................... 34
SYNC Input Network........................................ 35
Output Phase Noise Characteristics................ 36
Output Phase Synchronization of Multiple
ADF4382A Devices........................................ 36
Phase Synchronization Settings.......................37
Phase Resynchronization.................................39
Σ-Δ Modulator Optimization Modes..................... 40
Register Map....................................................... 41
Register Details................................................ 46
Outline Dimensions............................................. 82
Ordering Guide.................................................82
Evaluation Boards............................................ 82
REVISION HISTORY
10/2024—Rev. 0 to Rev. A
Changed Master to Main (Throughout)............................................................................................................1
Changes to Features Section.......................................................................................................................... 1
Changes to General Description......................................................................................................................1
Changes to Figure 1........................................................................................................................................ 1
Changes to Table 6........................................................................................................................................ 11
Changes to Typical Performance Characteristics Section............................................................................. 13
Added Figure 35; Renumbered Sequentially ................................................................................................ 17
Changes to Output Frequency Section..........................................................................................................20
Added Output Frequency Calculation Procedure Section............................................................................. 20
Changes to Table 9........................................................................................................................................22
Changes to Reference Divider (R) and Doubler (D) Section......................................................................... 22
Added Table 11; Renumbered Sequentially...................................................................................................22
Changes to Figure 45 ................................................................................................................................... 22
Change to Charge Pump Bleed Current Optimization Section...................................................................... 23
Changes to Bleed Current Modes Section.....................................................................................................23
Added Figure 46............................................................................................................................................ 24
Changes to Lock Detector Section................................................................................................................ 25
Changes to Temperature Sensor Section and Table 18................................................................................ 26
Changes to VCO Calibration Section.............................................................................................................27
Changes to Total Autocalibration Time Section............................................................................................. 28
Changes to Calibration Time Performance Consideration Section................................................................29
Added CAL_VTUNE_TO Time Calculation Section.......................................................................................29
Changes to Core Bias Table Section............................................................................................................. 29
Changes to RF Output Divider (O) Section....................................................................................................29
Changes to Feedback Divider (N) Section.....................................................................................................29
Added SYNC Monitor Section........................................................................................................................30
Changes to RF Output Buffer Section........................................................................................................... 31



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