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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LSM6DSV80X датащи(PDF) 30 Page - STMicroelectronics |
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LSM6DSV80X датащи(HTML) 30 Page - STMicroelectronics |
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30 / 181 page  Command Command code Default Description GETMXDS 0x94 0x08 0x60 Return max write and read speed GETCAPS 0x95 0x00 0x11 0x18 0x00 Provide information about device capabilities and supported extended features SETGRPA 0x9B Group address assignment command RSTGRPA 0x2C / 0x9C Reset the group address RSTACT 0x9A / 0x2A Configure target reset action 5.2.3 Overview of antispike filter management The device acts as a standard I²C target as long as it has an I²C static address. The device is capable of detecting and disabling the I²C antispike filter after detecting the broadcast address (7'h7E/W). In order to guarantee proper behavior of the device, the I3C controller must emit the first START, 7'h7E/W at open-drain speed using I²C fast mode plus reference timing. After detecting the broadcast address, the device can receive the I3C dynamic address following the I3C push- pull timing. If the device is not assigned a dynamic address, then the device continues to operate as an I²C device with no antispike filter. For the case in which the host decides to keep the device as I²C with an antispike filter, there is a configuration required to keep the antispike filter active. This configuration is done by writing the ASF_CTRL bit to 1 in the IF_CFG (03h) register. This configuration forces the antispike filter to always be turned on instead of being managed by the communication on the bus. 5.3 I²C controller interface If the LSM6DSV80X is configured in mode 2, an I²C controller line is available. The controller serial interface is mapped to the following dedicated pins. Table 18. I²C controller pin details Pin name Pin description CSCL I²C controller serial clock CSDA I²C controller serial data CDRDY I²C controller external synchronization signal LSM6DSV80X Digital interfaces DS14764 - Rev 1 page 30/181 |
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