MPC8280 datasheet(190/1386 Pages) FREESCALE

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System Interface Unit (SIU)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

4-18

Freescale Semiconductor

The SICR register bits are described in Table 4-4.

4.3.1.2

SIU Interrupt Priority Register (SIPRR)

The SIU interrupt priority register (SIPRR), shown in Figure 4-11, defines the priority between

IRQ1–IRQ5, PIT, PCI, and TMCNT.

Table 4-4. SICR Field Descriptions

Bits

Name

Description

0–1

—

Reserved, should be cleared.

2–7

Highest priority. Specifies the 6-bit interrupt number of the single interrupt controller interrupt source

that is advanced to the highest priority in the table. HP can be modified dynamically. To retain the

original priority, program HP to the interrupt number assigned to XSIU1. Port C interrupts have a fixed

priority level and cannot be advanced to the highest priority level.

8–13

—

Reserved, should be cleared.

GSIU Group SIU. Selects the relative XSIU priority scheme. It cannot be changed dynamically.

0 Grouped. The XSIUs are grouped by priority at the top of the table.

1 Spread. The XSIUs are spread by priority in the table.

SPS

Spread priority scheme. Selects the relative YCC priority scheme. It cannot be changed dynamically.

0 Grouped. The YCCs are grouped by priority at the top of the table.

1 Spread. The YCCs are spread by priority in the table.

Field

XS1P

XS2P

XS3P

XS4P

—

Reset

000

001

010

011

0000

R/W

Addr

0x10C10

Field

XS5P

XS6P

XS7P

XS8P

—

Reset

100

101

110

111

0000

R/W

Addr

0x10C12

Figure 4-11. SIU Interrupt Priority Register (SIPRR)

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