MPC8280 datasheet(188/1386 Pages) FREESCALE

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System Interface Unit (SIU)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

4-16

Freescale Semiconductor

Note that the interrupt vector table differs from the interrupt priority table in only two ways:

•

FCC, SCC, and MCC vectors are fixed; they are not affected by the SCC group mode, spread mode,

or the relative priority order of the FCCs, SCCs, and MCC.

•

An error vector exists as the last entry in Table 4-3. The error vector is issued when no interrupt is

requesting service.

4.2.4.1

Port C External Interrupts

There are 16 external interrupts, coming from the parallel I/O port C pins, PC[0–15]. When ones of these

pins is configured as an input, a change according to the SIU external interrupt control register (SIEXR)

causes an interrupt request signal to be sent to the interrupt controller. PC[0–15] lines can be programmed

to assert an interrupt request upon any change. Each port C line asserts a unique interrupt request to the

interrupt pending register and has a different internal interrupt priority level within the interrupt controller.

Requests can be masked independently in the interrupt mask register (SIMR). Notice that the global SIMR

is cleared on system reset so pins left floating do not cause false interrupts.

TC Layer1

0b10_1100

45–47

Reserved

0b10_11xx

PC15

0b11_0000

PC14

0b11_0001

PC13

0b11_0010

PC12

0b11_0011

PC11

0b11_0100

PC10

0b11_0101

PC9

0b11_0110

PC8

0b11_0111

PC7

0b11_1000

PC6

0b11_1001

PC5

0b11_1010

PC4

0b11_1011

PC3

0b11_1100

PC2

0b11_1101

PC1

0b11_1110

PC0

0b11_1111

1 MPC8280 only.

Table 4-3. Encoding the Interrupt Vector (continued)

Interrupt Number

Interrupt Source Description

Interrupt Vector

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