MPC8280 datasheet(189/1386 Pages) FREESCALE

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System Interface Unit (SIU)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

4-17

4.3

Programming Model

The SIU registers are grouped into the following three categories:

•

Interrupt controller registers. These registers control configuration, prioritization, and masking of

interrupts. They also include registers for determining the interrupt sources. These registers are

described in Section 4.3.1, “Interrupt Controller Registers.”

•

System configuration and protection registers. These include registers for configuring the SIU,

defining the base address for the internal memory map, configuring the watchdog timer, specifying

bus characteristics, as well as general functionality of the 60x, and local buses such as arbitration,

error status, and control. These registers are described in Section 4.3.2, “System Configuration and

Protection Registers.”

•

Periodic interrupt registers. These include registers for configuring and providing status for

periodic interrupts. See Section 4.3.3, “Periodic Interrupt Registers.”

4.3.1

Interrupt Controller Registers

There are seven interrupt controller registers, described in the following sections:

•

Section 4.3.1.1, “SIU Interrupt Configuration Register (SICR)”

•

Section 4.3.1.2, “SIU Interrupt Priority Register (SIPRR)”

•

Section 4.3.1.3, “CPM Interrupt Priority Registers (SCPRR_H and SCPRR_L)”

•

Section 4.3.1.4, “SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L)”

•

Section 4.3.1.5, “SIU Interrupt Mask Registers (SIMR_H and SIMR_L)”

•

Section 4.3.1.6, “SIU Interrupt Vector Register (SIVEC)”

•

Section 4.3.1.7, “SIU External Interrupt Control Register (SIEXR)”

4.3.1.1

SIU Interrupt Configuration Register (SICR)

The SIU interrupt configuration register (SICR), shown in Figure 4-10, defines the highest priority

interrupt and whether interrupts are grouped or spread in the priority table, Table 4-2.

131415

Field

—

GSIU

SPS

Reset

0000_0000_0000_0000

R/W

Addr

0x10C00

Figure 4-10. SIU Interrupt Configuration Register (SICR)

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