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MPC8280 датащи(PDF) 185 Page - Freescale Semiconductor, Inc |
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MPC8280 датащи(HTML) 185 Page - Freescale Semiconductor, Inc |
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185 / 1386 page ![]() System Interface Unit (SIU) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 4-13 • Spread. In the spread scheme, priorities are spread over the table so other sources can have lower interrupt latencies. This scheme is also programmed in the SICR but cannot be changed dynamically. 4.2.2.2 PIT, TMCNT, PCI, and IRQ Relative Priority The MPC8280 has seven general-purpose interrupt requests (IRQs), five of which, with the PIT, the PCI interrupt controller, and TMCNT, can be mapped to any XSIU location. IRQ6 and IRQ7 have fixed priority. 4.2.2.3 Highest Priority Interrupt In addition to the FCC/MCC/SCC relative priority option, SICR[HP] can be used to specify one interrupt source as having highest priority. This interrupt remains within the same interrupt level as the other interrupt controller interrupts, but is serviced before any other interrupt in the table. If the highest priority feature is not used, select the interrupt request in XSIU1 to be the highest priority interrupt; the standard interrupt priority order is used. SICR[HP] can be updated dynamically to allow the user to change a normally low priority source into a high priority-source for a certain period. 4.2.3 Masking Interrupt Sources By programming the SIU mask registers, SIMR_H and SIMR_L, the user can mask interrupt requests to the core. Each SIMR bit corresponds to an interrupt source. To enable an interrupt, set the corresponding SIMR bit. When a masked interrupt source has a pending interrupt request, the corresponding SIPNR bit is set, even though the interrupt is not generated to the core. The user can mask all interrupt sources to implement a polling interrupt servicing scheme. When an interrupt source has multiple interrupting events, the user can individually mask these events by programming a mask register within that block. Table 4-2 shows which interrupt sources have multiple interrupting events. Figure 4-9 shows an example of how the masking occurs, using an SCC as an example. |
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