MPC8280 datasheet(158/1386 Pages) FREESCALE

158 / 1386 page

Memory Map

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

3-14

Freescale Semiconductor

0x11391–

0x1139F

Reserved

—

15 bytes

—

FCC2 Extended Registers

0x113A0

FCC2 internal rate port enable register (FIRPER2)

R/W

32 bits

0x0000_0000

31.15.1.4/31-93

0x113A4

FCC2 internal rate event register (FIRER2)

R/W

32 bits

0x0000_0000

31.15.1.5/31-94

0x113A8

FCC2 internal rate select register high (FIRSR2_HI)

R/W

32 bits

0x0000_0000

31.15.1.6/31-95

0x113AC

FCC2 internal rate select register low (FIRSR2_LO)

R/W

32 bits

0x0000_0000

31.15.1.6/31-95

0x113B0

FCC2 general expansion mode register (GFEMR2)

R/W

8 bits

0x00

30.2.1/30-7

0x113B1–

0x113CF

Reserved

—

31 bytes

—

FCC3 Extended Registers

0x113D0

General FCC3 expansion mode register (GFEMR3)

R/W

8 bits

0x00

30.2.1/30-7

0x113D1

Reserved

—

47 bytes

—

TC Layer 11

0x11400

TC1 mode register (TCMODE1)1

R/W

16 bits

0x0000

35.4.1.1/35-7

0x11402

TC1 cell delineation state machine register (CDSMR1)1

R/W

16 bits

0x0000

35.4.1.2/35-8

0x11404

TC1 event register (TCER1)1

R/W

16 bits

0x0000

35.4.1.3/35-9

0x11406

TC1 received cells counter (TC_RCC1)1

R/W

16 bits

0x0000

35.4.1.4/35-10

0x11408

TC1 mask register (TCMR1)1

R/W

16 bits

0x0000

35.4.1.4/35-10

0x1140A

TC1 filtered cells counter (TC_FCC1)1

R/W

16 bits

0x0000

35.4.3.6/35-12

0x1140C

TC1 corrected cells counter (TC_CCC1)1

R/W

16 bits

0x0000

35.4.3.4/35-12

0x1140E

TC1 idle cells counter (TC_ICC1)1

R/W

16 bits

0x0000

35.4.3.5/35-12

0x11410

TC1 transmitted cells counter (TC_TCC1)1

R/W

16 bits

0x0000

35.4.3.2/35-11

0x11412

TC1 error cells counter (TC_ECC1)1

R/W

16 bits

0x0000

35.4.3.3/35-12

0x11414

Reserved

—

12 bytes

—

TC Layer 21

0x11420

TC2 mode register (TCMODE2)1

R/W

16 bits

0x0000

35.4.1.1/35-7

0x11422

TC2 cell delineation state machine register (CDSMR2)1

R/W

16 bits

0x0000

35.4.1.2/35-8

0x11424

TC2 event register (TCER2)1

R/W

16 bits

0x0000

35.4.1.3/35-9

0x11426

TC2 received cells counter (TC_RCC2)1

R/W

16 bits

0x0000

35.4.1.4/35-10

0x11428

TC2 mask register (TCMR2)1

R/W

16 bits

0x0000

35.4.1.4/35-10

0x1142A

TC2 filtered cells counter (TC_FCC2)1

R/W

16 bits

0x0000

35.4.3.6/35-12

Table 3-1. Internal Memory Map (continued)

Address

(offset)

R/W

Size

Reset

Section/Page

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