MPC8280 datasheet(157/1386 Pages) FREESCALE

157 / 1386 page

Memory Map

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

3-13

FCC3

0x11340

FCC3 general mode register (GFMR3)

R/W

32 bits

0x0000_0000

30.2/30-3

0x11344

FCC3 protocol-specific mode register (FPSMR3)

R/W

32 bits

0x0000_0000

31.13.2/31-85

(ATM)

34.4.2.1.1/34-2

(IMA)

36.18.1/36-19

(Ethernet)

37.6/37-8

(HDLC)

0x11348

FCC3 transmit on-demand register (FTODR3)

R/W

16 bits

0x0000

30.5/30-9

0x1134A

Reserved

—

16 bits

—

0x1134C

FCC3 data synchronization register (FDSR3)

R/W

16 bits

0x7E7E

30.4/30-8

0x1134E

Reserved

—

16 bits

—

0x11350

FCC3 event register (FCCE3)

R/W

16 bits

0x0000

31.13.3/31-88

(ATM)

36.18.2/36-21

(Ethernet)

37.9/37-14

(HDLC)

0x11352

Reserved

—

16 bits

—

0x11354

FCC3 mask register (FCCM3)

R/W

16 bits

0x0000

31.13.3/31-88

(ATM)

36.18.2/36-21

(Ethernet)

37.9/37-14

(HDLC)

0x11356

Reserved

—

16 bits

—

0x11358

FCC3 status register (FCCS3)

16 bits

0x0000

37.10/37-16

(HDLC)

0x11359–

0x11379

Reserved

—

32 bytes

—

FCC1 Extended Registers

0x11380

FCC1 internal rate port enable register (FIRPER1)

—

32 bit

0x0000_0000

31.15.1.4/31-93

0x11384

FCC1 internal rate event register (FIRER1)

—

32 bit

0x0000_0000

31.15.1.5/31-94

0x11388

FCC1 internal rate select register high (FIRSR1_HI)

—

32 bit

0x0000_0000

31.15.1.6/31-95

0x1138C

FCC1 internal rate select register low (FIRSR1_LO)

—

32 bit

0x0000_0000

31.15.1.6/31-95

0x11390

FCC1 general extended mode register (GFEMR1)

—

8 bit

0x00

30.2.1/30-7

Table 3-1. Internal Memory Map (continued)

Address

(offset)

R/W

Size

Reset

Section/Page

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