MPC8280 datasheet(156/1386 Pages) FREESCALE

156 / 1386 page

Memory Map

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

3-12

Freescale Semiconductor

FCC2

0x11320

FCC2 general mode register (GFMR2)

R/W

32 bits

0x0000_0000

30.2/30-3

0x11324

FCC2 protocol-specific mode register (FPSMR2)

R/W

32 bits

0x0000_0000

31.13.2/31-85

(ATM)

34.4.2.1.1/34-2

(IMA)

36.18.1/36-19

(Ethernet)

37.6/37-8

(HDLC)

0x11328

FCC2 transmit on-demand register (FTODR2)

R/W

16 bits

0x0000

30.5/30-9

0x1132A

Reserved

—

16 bits

—

0x1132C

FCC2 data synchronization register (FDSR2)

R/W

16 bits

0x7E7E

30.4/30-8

0x1132E

Reserved

—

16 bits

—

0x11330

FCC2 event register (FCCE2)

R/W

16 bits

0x0000_0000

31.13.3/31-88

(ATM)

36.18.2/36-21

(Ethernet)

37.9/37-14

(HDLC)

0x11332

Reserved

—

16 bits

—

0x11334

FCC2 mask register (FCCM2)

R/W

16 bits

0x0000_0000

31.13.3/31-88

(ATM)

36.18.2/36-21

(Ethernet)

37.9/37-14

(HDLC)

0x11336

Reserved

—

16 bits

—

0x11338

FCC2 status register (FCCS2)

16 bits

0x00

37.10/37-16

(HDLC)

0x11339

Reserved

—

24 bits

—

0x1133C

FCC2 transmit internal rate registers for PHY0

(FTIRR2_PHY0)

R/W

8 bits

0x00

31.15.1.4/31-93

(ATM)

34.4.2.1.2/34-2

(IMA)

0x1133D

FCC2 transmit internal rate registers for PHY1

(FTIRR2_PHY1)

R/W

8 bits

0x00

0x11133E FCC2 transmit internal rate registers for PHY2

(FTIRR2_PHY2)

R/W

8 bits

0x00

0x1133F

FCC2 transmit internal rate registers for PHY3

(FTIRR2_PHY3)

R/W

8 bits

0x00

Table 3-1. Internal Memory Map (continued)

Address

(offset)

R/W

Size

Reset

Section/Page

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