MPC8280 datasheet(162/1386 Pages) FREESCALE

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Memory Map

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

3-18

Freescale Semiconductor

0x1186D

Reserved

—

24 bits

—

0x11870

I2C event register (I2CER)

R/W

8 bits

0x00

40.4.4/40-7

0x11871

Reserved

—

24 bits

—

0x11874

I2C mask register (I2CMR)

R/W

8 bits

0x00

40.4.4/40-7

0x11875–

0x119BF

Reserved

—

315

bytes

——

Communications Processor

0x119C0

Communications processor command register (CPCR)

R/W

32 bits

0x0000_0000

14.4.1/14-12

0x119C4

CP configuration register (RCCR)

R/W

32 bits

0x0000_0000

14.3.7/14-9

0x119C8–

0x119D5

Reserved

—

14 bytes

—

0x119D6

CP timers event register (RTER)

R/W

16 bits

0x0000_0000

14.6.4/14-25

0x119DA

CP timers mask register (RTMR)

R/W

16 bits

0x0000_0000

0x119DC

CP time-stamp timer control register (RTSCR)

—

16 bits

0x0000

14.3.8/14-10

0x119DE

Reserved

R/W

16 bits

—

0x119E0

CP time-stamp register (RTSR)

R/W

32 bits

0x0000

14.3.9/14-11

BRGs 1–4

0x119F0

BRG1 configuration register (BRGC1)

R/W

32 bits

0x0000_0000

17.1/17-2

0x119F4

BRG2 configuration register (BRGC2)

R/W

32 bits

0x0000_0000

0x119F8

BRG3 configuration register (BRGC3)

R/W

32 bits

0x0000_0000

0x119FC

BRG4 configuration register (BRGC4)

R/W

32 bits

0x0000_0000

SCC1

0x11A00

SCC1 general mode register (GSMR_L1)

R/W

32 bits

0x0000_0000

20.1.1/20-3

0x11A04

SCC1 general mode register (GSMR_H1)

R/W

32 bits

0x0000_0000

0x11A08

SCC1 protocol-specific mode register (PSMR1)

R/W

16 bits

0x0000

20.1.2/20-9

21.16/21-13

(UART)

22.8/22-7

(HDLC)

23.11/23-10

(BISYNC)

24.9/24-8

(Transparent)

25.17/25-14

(Ethernet)

0x11A0A

Reserved

—

16 bits

—

Table 3-1. Internal Memory Map (continued)

Address

(offset)

R/W

Size

Reset

Section/Page

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