MPC8280 datasheet(121/1386 Pages) FREESCALE

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G2_LE Core

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

2-5

•

Deterministic behavior and debug features

— On-chip cache locking options for the instruction and data caches (1–3 ways or the entire cache

contents can be locked)

— In-system testability and debugging features through JTAG and boundary-scan capability

Features supported by the G2_LE core not present on the MPC8280:

•

True little-endian mode for compatibility with other true little-endian devices

•

Nap and sleep power-saving modes

Figure 2-1 shows how the execution units—IU, BPU, LSU, and SRU—operate independently and in

parallel. Note that this is a conceptual diagram and does not attempt to show how these features are

physically implemented on the chip.

The processor core provides address translation and protection facilities, including an ITLB, DTLB, and

instruction and data BAT arrays. Instruction fetching and issuing is handled in the instruction unit. The

MMUs translate addresses for cache or external memory accesses.

2.2.1

Instruction Unit

As shown in Figure 2-1, the instruction unit, which contains a fetch unit, instruction queue, dispatch unit,

and the BPU, provides centralized control of instruction flow to the execution units. The instruction unit

determines the address of the next instruction to be fetched based on information from the sequential

fetcher and from the BPU.

The instruction unit fetches the instructions from the instruction cache into the instruction queue. The BPU

extracts branch instructions from the fetcher and uses static branch prediction on unresolved conditional

branches to allow the instruction unit to fetch instructions from a predicted target instruction stream while

a conditional branch is evaluated. The BPU folds out branch instructions for unconditional branches or

conditional branches unaffected by instructions in progress in the execution pipeline.

Instructions issued beyond a predicted branch do not complete execution until the branch is resolved,

preserving the programming model of sequential execution. If any of these instructions are to be executed

in the BPU, they are decoded but not issued. Instructions to be executed by the IU, LSU, and SRU are

issued and allowed to complete up to the register write-back stage. Write-back is allowed when a correctly

predicted branch is resolved, and instruction execution continues without interruption on the predicted

path. If branch prediction is incorrect, the instruction unit flushes all predicted path instructions, and

instructions are issued from the correct path.

2.2.2

Instruction Queue and Dispatch Unit

The instruction queue (IQ), shown in Figure 2-1, holds as many as six instructions and loads up to two

instructions from the instruction unit during a single cycle. The instruction fetch unit continuously loads

as many instructions as space in the IQ allows. Instructions are dispatched to their respective execution

units from the dispatch unit at a maximum rate of two instructions per cycle. Reservation stations at the

IU, LSU, and SRU facilitate instruction dispatch to those units. The dispatch unit checks for source and

destination register dependencies, determines dispatch serializations, and inhibits subsequent instruction

dispatching as required. Section 2.7, “Instruction Timing,” describes instruction dispatch in detail.

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